MC68HC908GR4MP datasheet(177/286 Pages) FREESCALE

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I/O Registers

MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7

Freescale Semiconductor

177

18.8.2 SCI Control Register 2

SCI control register 2:

•

Enables the following CPU interrupt requests:

–

Enables the SCTE bit to generate transmitter CPU interrupt requests

–

Enables the TC bit to generate transmitter CPU interrupt requests

–

Enables the SCRF bit to generate receiver CPU interrupt requests

–

Enables the IDLE bit to generate receiver CPU interrupt requests

•

Enables the transmitter

•

Enables the receiver

•

Enables SCI wakeup

•

Transmits SCI break characters

SCTIE — SCI Transmit Interrupt Enable Bit

This read/write bit enables the SCTE bit to generate SCI transmitter CPU interrupt requests. Reset

clears the SCTIE bit.

1 = SCTE enabled to generate CPU interrupt

0 = SCTE not enabled to generate CPU interrupt

TCIE — Transmission Complete Interrupt Enable Bit

This read/write bit enables the TC bit to generate SCI transmitter CPU interrupt requests. Reset clears

the TCIE bit.

1 = TC enabled to generate CPU interrupt requests

0 = TC not enabled to generate CPU interrupt requests

SCRIE — SCI Receive Interrupt Enable Bit

This read/write bit enables the SCRF bit to generate SCI receiver CPU interrupt requests. Reset clears

the SCRIE bit.

1 = SCRF enabled to generate CPU interrupt

0 = SCRF not enabled to generate CPU interrupt

Table 18-5. Character Format Selection

Control Bits

Character Format

PEN and PTY

Start Bits

Data Bits

Parity

Stop Bits

Character Length

None

10 bits

None

11 bits

Even

10 bits

Odd

10 bits

Even

11 bits

Odd

11 bits

Address:

$0014

Bit 7

654321

Bit 0

Read:

SCTIE

TCIE

SCRIE

ILIE

RWU

SBK

Write:

Reset:

00000000

Figure 18-10. SCI Control Register 2 (SCC2)

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