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P89V52X2FN Datasheet(PDF) 48 Page - NXP Semiconductors |
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P89V52X2FN Datasheet(HTML) 48 Page - NXP Semiconductors |
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48 / 56 page ![]() P89V52X2_1 © NXP B.V. 2007. All rights reserved. Preliminary data sheet Rev. 01 — 7 June 2007 48 of 56 NXP Semiconductors P89V52X2 80C51 with 256 B RAM, 192 B data EEPROM Fig 25. Shift register mode timing waveforms 002aaa552 ALE 0 instruction 1 2 3 4 5 6 7 8 0 1 23 45 6 7 valid valid valid valid valid valid valid valid tXLXL set TI set RI tXHQX tQVXH tXHDV tXHDX clock output data write to SBUF input data clear RI Fig 26. Test load example All other pins disconnected Fig 27. IDD test condition, active mode 002aaa555 to DUT to tester CL 002aaa556 VDD VDD VDD P0 EA RST XTAL2 (n.c.) clock signal XTAL1 VSS IDD VDD 8 |
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