P89V52X2FN datasheet(16/56 Pages) PHILIPS

16 / 56 page

P89V52X2_1

Preliminary data sheet

Rev. 01 — 7 June 2007

16 of 56

NXP Semiconductors

P89V52X2

80C51 with 256 B RAM, 192 B data EEPROM

Table 11.

TMOD - Timer/Counter mode control register (address 89H) bit description

Bit

Symbol

Description

T1GATE

Gating control for Timer 1. When set, Timer/Counter is enabled only

while the INT1 pin is high and the TR1 control pin is set. When

cleared, Timer 1 is enabled when the TR1 control bit is set.

6T1C/T

Timer or Counter select for Timer 1. Cleared for Timer operation (input

from CCLK). Set for Counter operation (input from T1 input pin).

T1M1

Mode select for Timer 1.

4T1M0

T0GATE

Gating control for Timer 0. When set, Timer/Counter is enabled only

while the INT0 pin is high and the TR0 control pin is set. When

cleared, Timer 0 is enabled when the TR0 control bit is set.

2T0C/T

Timer or Counter select for Timer 0. Cleared for Timer operation (input

from CCLK). Set for Counter operation (input from T0 input pin).

T0M1

Mode Select for Timer 0.

0T0M0

Table 12.

TMOD - Timer/Counter mode control register (address 89H) M1/M0 operating

mode

Operating mode

8048 timer ‘TLx’ serves as 5-bit prescaler

16-bit Timer/Counter ‘THx’ and ‘TLx' are cascaded;

there is no prescaler.

8-bit auto-reload Timer/Counter ‘THx’ holds a value

which is to be reloaded into ‘TLx’ each time it

overflows.

(Timer 0) TL0 is an 8-bit Timer/Counter controlled

by the standard Timer 0 control bits. TH0 is an 8-bit

timer only controlled by Timer 1 control bits.

(Timer 1) Timer/Counter 1 stopped.

Table 13.

TCON - Timer/Counter control register (address 88H) bit allocation

Bit addressable; Reset value: 0000 0000B; Reset source(s): any reset

Bit

Symbol

TF1

TR1

TF0

TR0

IE1

IT1

IE0

IT0

Table 14.

TCON - Timer/Counter control register (address 88H) bit description

Bit

Symbol

Description

TF1

Timer 1 overflow flag. Set by hardware on Timer/Counter overflow.

Cleared by hardware when the processor vectors to Timer 1 Interrupt

routine, or by software.

TR1

Timer 1 Run control bit. Set/cleared by software to turn Timer/Counter

1 on/off.

TF0

Timer 0 overflow flag. Set by hardware on Timer/Counter overflow.

Cleared by hardware when the processor vectors to Timer 0 Interrupt

routine, or by software.

TR0

Timer 0 Run control bit. Set/cleared by software to turn Timer/Counter

0 on/off.

P89V52X2FN Datasheet(PDF) 16 Page - NXP Semiconductors

P89V52X2FN Datasheet(HTML) 16 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56

Datasheet Download

Link URL