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P89V52X2FN Datasheet(PDF) 56 Page - NXP Semiconductors

Part # P89V52X2FN
Description  8-bit 80C51 low power 8 kB flash microcontroller with 256 B RAM, 192 B data EEPROM
PDF  56 Pages
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Manufacturer  PHILIPS [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

P89V52X2FN Datasheet(HTML) 56 Page - NXP Semiconductors

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NXP Semiconductors
P89V52X2
80C51 with 256 B RAM, 192 B data EEPROM
© NXP B.V. 2007.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 7 June 2007
Document identifier: P89V52X2_1
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
15. Contents
1
General description . . . . . . . . . . . . . . . . . . . . . . 1
2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2.1
Principal features . . . . . . . . . . . . . . . . . . . . . . . 1
2.2
Additional features . . . . . . . . . . . . . . . . . . . . . . 1
3
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
3.1
Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2
4
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2
5
Pinning information . . . . . . . . . . . . . . . . . . . . . . 3
5.1
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
5.2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5
6
Functional description . . . . . . . . . . . . . . . . . . . 8
6.1
Special function registers . . . . . . . . . . . . . . . . . 8
6.2
Memory organization . . . . . . . . . . . . . . . . . . . 11
6.3
System clock and clock options . . . . . . . . . . . 11
6.3.1
Clock input options and recommended capacitor
values for the oscillator . . . . . . . . . . . . . . . . . . 11
6.3.2
Clock control register (CKCON) . . . . . . . . . . . 12
6.4
ALE control . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
6.5
Dual data pointers. . . . . . . . . . . . . . . . . . . . . . 13
6.6
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.7
Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . 15
6.7.1
Flash organization . . . . . . . . . . . . . . . . . . . . . 15
6.7.2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6.8
Timers/counters 0 and 1 . . . . . . . . . . . . . . . . . 15
6.8.1
Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.8.2
Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.8.3
Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.8.4
Mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.9
Timer 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.9.1
Capture mode . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.9.2
Auto-reload mode (up or down-counter). . . . . 21
6.9.3
Programmable clock-out. . . . . . . . . . . . . . . . . 23
6.9.4
Baud rate generator mode . . . . . . . . . . . . . . . 23
6.9.5
Summary of baud rate equations . . . . . . . . . . 25
6.10
UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6.10.1
Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6.10.2
Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.10.3
Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.10.4
Mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.10.5
Framing error . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.10.6
More about UART mode 1 . . . . . . . . . . . . . . . 27
6.10.7
More about UART modes 2 and 3 . . . . . . . . . 27
6.10.8
Multiprocessor communications . . . . . . . . . . . 28
6.10.9
Automatic address recognition . . . . . . . . . . . . 28
6.11
Interrupt priority and polling sequence . . . . . . 30
6.12
Power-saving modes . . . . . . . . . . . . . . . . . . . 32
6.12.1
Idle mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6.12.2
Power-down mode . . . . . . . . . . . . . . . . . . . . . 33
6.13
Data EEPROM . . . . . . . . . . . . . . . . . . . . . . . . 33
6.13.1
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.13.2
Register interface. . . . . . . . . . . . . . . . . . . . . . 34
6.13.3
Mapping the data EEPROM into code space. 34
6.13.4
Reading the data EEPROM . . . . . . . . . . . . . . 34
6.13.5
Erasing a complete page (64 B) . . . . . . . . . . 35
6.13.6
Data EEPROM programming and erasing using
the page register . . . . . . . . . . . . . . . . . . . . . . 35
6.13.7
Data EEPROM write enable . . . . . . . . . . . . . 39
6.13.8
Data EEPROM security bits . . . . . . . . . . . . . . 39
6.13.9
Summary of data EEPROM commands . . . . 39
6.14
User configuration bytes . . . . . . . . . . . . . . . . 40
6.15
UCFG. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
6.16
Code security (CSEC) bits . . . . . . . . . . . . . . . 41
7
Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 42
8
Static characteristics . . . . . . . . . . . . . . . . . . . 42
9
Dynamic characteristics. . . . . . . . . . . . . . . . . 44
9.1
Explanation of symbols . . . . . . . . . . . . . . . . . 45
10
Package outline. . . . . . . . . . . . . . . . . . . . . . . . 50
11
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 53
12
Revision history . . . . . . . . . . . . . . . . . . . . . . . 54
13
Legal information . . . . . . . . . . . . . . . . . . . . . . 55
13.1
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 55
13.2
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
13.3
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 55
13.4
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 55
14
Contact information . . . . . . . . . . . . . . . . . . . . 55
15
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56



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