P89V52X2FN datasheet(33/56 Pages) PHILIPS

33 / 56 page

P89V52X2_1

Preliminary data sheet

Rev. 01 — 7 June 2007

33 of 56

NXP Semiconductors

P89V52X2

80C51 with 256 B RAM, 192 B data EEPROM

The device exits Idle mode through either a system interrupt or a hardware reset. Exiting

Idle mode via system interrupt, the start of the interrupt clears the IDL bit and exits Idle

mode. After exit the Interrupt Service Routine, the interrupted program resumes execution

beginning at the instruction immediately following the instruction which invoked the Idle

mode. A hardware reset starts the device similar to a power-on reset.

6.12.2 Power-down mode

The Power-down mode is entered by setting the PD bit in the PCON register. In the

Power-down mode, the clock is stopped and external interrupts are active for level

sensitive interrupts only. SRAM contents are retained during Power-down, the minimum

VDD level is 2.0 V.

The device exits Power-down mode through either an enabled external level sensitive

interrupt or a hardware reset. The start of the interrupt clears the PD bit and exits

Power-down. Holding the external interrupt pin low restarts the oscillator, the signal must

hold low at least 1024 clock cycles before bringing back high to complete the exit. Upon

interrupt signal restored to logic VIH, the interrupt service routine program execution

resumes beginning at the instruction immediately following the instruction which invoked

Power-down mode. A hardware reset starts the device similar to power-on reset.

To exit properly out of Power-down, the reset or external interrupt should not be executed

before the VDD line is restored to its normal operating voltage. Be sure to hold VDD voltage

long enough at its normal operating level for the oscillator to restart and stabilize (normally

less than 10 ms).

6.13 Data EEPROM

The P89V52X2 contains 192 B of data EEPROM organized into three pages of 64 B each.

This memory can be erased in 64 byte pages (using a Page Erase command) or erased

and written as bytes. The P89V52X2 flash reliably stores memory contents even after

100000 erase and program cycles. The cell is designed to optimize the erase and

programming mechanisms. P89V52X2 uses VDD as the supply voltage to perform the

Program/Erase algorithms.

Table 31.

Power-saving modes

Mode

Initiated by

State of device

Exited by

Idle mode

Software

(Set IDL bit in PCON)

MOV PCON, #01H;

CLK is running.

Interrupts, serial port and

timers/counters are active.

Program Counter is stopped.

ALE and PSEN signals at a

HIGH-level during Idle. All

registers remain unchanged.

Enabled interrupt or hardware reset. Start of

interrupt clears IDL bit and exits Idle mode,

after the ISR RETI instruction, program

resumes execution beginning at the

instruction following the one that invoked

Idle mode. A hardware reset restarts the

device similar to a power-on reset.

Power-down

mode

Software

(Set PD bit in PCON)

MOV PCON, #02H;

CLK is stopped. On-chip SRAM

and SFR data is maintained.

ALE and PSEN signals at a

LOW-level during power-down.

External Interrupts are only

active for level sensitive

interrupts, if enabled.

Enabled external level sensitive interrupt or

hardware reset. Start of interrupt clears PD

bit and exits Power-down mode, after the

ISR RETI instruction program resumes

execution beginning at the instruction

following the one that invoked Power-down

mode. A hardware reset restarts the device

similar to a power-on reset.

P89V52X2FN Datasheet(PDF) 33 Page - NXP Semiconductors

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