P89V52X2FN datasheet(19/56 Pages) PHILIPS

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P89V52X2_1

Preliminary data sheet

Rev. 01 — 7 June 2007

19 of 56

NXP Semiconductors

P89V52X2

80C51 with 256 B RAM, 192 B data EEPROM

6.9 Timer 2

Timer 2 is a 16-bit Timer/Counter which can operate as either an event timer or an event

counter, as selected by C/T2 in the special function register T2CON. Timer 2 has four

operating modes: Capture, Auto-reload (up or down counting), Clock-out, and Baud Rate

Generator which are selected according to Table 15 using T2CON (Table 16 and

Table 17) and T2MOD (Table 18 and Table 19).

Fig 13. Timer/Counter 0 Mode 3 (two 8-bit counters)

002aaa522

osc/2

TR1

TR0

TnGate

INT0 pin

TL0

(8-bits)

TF0

control

overflow

interrupt

TH0

(8-bits)

TF1

control

overflow

interrupt

osc/6

T0 pin

C/T = 0

C/T = 1

Table 15.

Timer 2 operating mode

RCLK+TCLK

CP/RL2

TR2

T2OE

Mode

16-bit auto reload

16-bit capture

Programmable Clock-Out

Baud rate generator

off

Table 16.

T2CON - Timer/Counter 2 control register (address C8H) bit allocation

Bit addressable; Reset value: 00H

Bit

Symbol

TF2

EXF2

RCLK

TCLK

EXEN2

TR2

C/T2CP/RL2

Table 17.

T2CON - Timer/Counter 2 control register (address C8H) bit description

Bit

Symbol

Description

TF2

Timer 2 overflow flag set by a Timer 2 overflow and must be cleared by

software. TF2 will not be set when either RCLK or TCLK = 1 or when

Timer 2 is in Clock-out mode.

EXF2

Timer 2 external flag is set when Timer 2 is in capture, reload or baud

rate mode, EXEN2 = 1 and a negative transition on T2EX occurs. If

Timer 2 interrupt is enabled EXF2 = 1 causes the CPU to vector to the

Timer 2 interrupt routine. EXF2 must be cleared by software.

RCLK

Receive clock flag. When set, causes the UART to use Timer 2

overflow pulses for its receive clock in modes 1 and 3. RCLK = 0

causes Timer 1 overflow to be used for the receive clock.

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