P89V52X2FN datasheet(12/56 Pages) PHILIPS

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P89V52X2_1

Preliminary data sheet

Rev. 01 — 7 June 2007

12 of 56

NXP Semiconductors

P89V52X2

80C51 with 256 B RAM, 192 B data EEPROM

6.3.2 Clock control register (CKCON)

By default, the device runs at twelve clocks per machine cycle. The device may be run in

6 clock per machine cycle mode by programming of either a non-volatile bit (FX2) or an

SFR bit (Table 5 “Clock modes”). If the FX2 non-volatile bit is programmed the device will

run in 6-clock mode and the X2 SFR bit has no effect. If the FX2 bit is erased, then the

clock mode is controlled by the X2 SFR bit.

6.4 ALE control

Fig 5.

Oscillator characteristics (using the on-chip oscillator)

Fig 6.

Oscillator characteristics (external clock drive)

002aaa545

XTAL2

XTAL1

VSS

002aaa546

XTAL2

n.c.

XTAL1

external

oscillator

signal

VSS

Table 5.

Clock modes

FX2 clock mode bit (UCFG.1)

X2 bit (CLKCON.0)

CPU clock mode

erased

12-clock mode (default)

erased

6-clock mode

programmed

6-clock mode

Table 6.

AUXR - Auxiliary register (address 8EH) bit allocation

Not bit addressable; Reset value 00H

Bit

Symbol

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