P89V52X2FN datasheet(14/56 Pages) PHILIPS

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P89V52X2_1

Preliminary data sheet

Rev. 01 — 7 June 2007

14 of 56

NXP Semiconductors

P89V52X2

80C51 with 256 B RAM, 192 B data EEPROM

6.6 Reset

At initial power-up, the port pins will be in a random state until the oscillator has started

and the internal reset algorithm has weakly pulled all pins high. Powering up the device

without a valid reset could cause the device to start executing instructions from an

indeterminate location. Such undefined states may inadvertently corrupt the code in the

flash. A system reset will not affect the on-chip RAM while the device is running, however,

the contents of the on-chip RAM during power-up are indeterminate.

When power is applied to the device, the RST pin must be held high long enough for the

oscillator to start-up (usually several milliseconds for a low frequency crystal), in addition

to two machine cycles for a valid power-on reset. An example of a method to extend the

RST signal is to implement a RC circuit by connecting the RST pin to VDD through a 10 µF

capacitor and to VSS through an 8.2 kΩ resistor as shown in Figure 9.

During initial power the POF flag in the PCON register is set to indicate an initial power-up

condition. The POF flag will remain active until cleared by software.

Following a reset condition, under normal conditions, the device will start executing code

from address 0000H in the user’s code memory. However if the requirements are met for

ICP entry, the device will enter ICP mode.

Table 9.

AUXR1 - Auxiliary register 1 (address A2H) bit description

Bit

Symbol

Description

7 to 4

Reserved for future use. Should be set to ‘0’ by user programs.

GF2

General purpose user-defined flag.

This bit contains a hard-wired ‘0’. Allows toggling of the DPS bit by

incrementing AUXR1, without interfering with other bits in the register.

Reserved for future use. Should be set to ‘0’ by user programs.

DPS

Data pointer select. Chooses one of two Data Pointers for use by the

program. See text for details.

Fig 9.

Power-on reset circuit

002aaa543

VDD

8.2 k

Ω

RST

XTAL2

XTAL1

µF

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