P89V52X2FN datasheet(30/56 Pages) PHILIPS

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P89V52X2_1

Preliminary data sheet

Rev. 01 — 7 June 2007

30 of 56

NXP Semiconductors

P89V52X2

80C51 with 256 B RAM, 192 B data EEPROM

(6)

Example 2, slave 1:

(7)

Example 2, slave 2:

(8)

In the above example the differentiation among the 3 slaves is in the lower 3 address bits.

Slave 0 requires that bit 0 = 0 and it can be uniquely addressed by 1110 0110. Slave 1

requires that bit 1 = 0 and it can be uniquely addressed by 1110 0101. Slave 2 requires

that bit 2 = 0 and its unique address is 1110 0011. To select Slaves 0 and 1 and exclude

Slave 2 use address 1110 0100, since it is necessary to make bit 2 = 1 to exclude slave 2.

The Broadcast Address for each slave is created by taking the logical OR of SADDR and

SADEN. Zeros in this result are treated as don’t-cares. In most cases, interpreting the

don’t-cares as ones, the broadcast address will be FF hexadecimal. Upon reset SADDR

and SADEN are loaded with 0s. This produces a given address of all ‘don’t cares’ as well

as a Broadcast address of all ‘don’t cares'. This effectively disables the Automatic

Addressing mode and allows the microcontroller to use standard UART drivers which do

not make use of this feature.

6.11 Interrupt priority and polling sequence

The device supports six interrupt sources under a four level priority scheme. Table 24

summarizes the polling sequence of the supported interrupts. (See Figure 19).

SADDR = 1100 0000

SADEN = 1111 1001

Given = 1100 0XX0

----------------------------------------------------

SADDR = 1110 0000

SADEN = 1111 1010

Given = 1110 0X0X

----------------------------------------------------

SADDR = 1100 0000

SADEN = 1111 1100

Given = 1100 00XX

----------------------------------------------------

Table 24.

Interrupt polling sequence

Description

Interrupt flag

Vector address Interrupt

enable

Interrupt

priority

Service

priority

Wake-up

Power-down

External

Interrupt 0

IE0

0003H

EX0

PX0/H

1 (highest)

yes

TF0

000BH

ET0

PT0/H

External

Interrupt 1

IE1

0013H

EX1

PX1/H

yes

TF1

001BH

ET1

PT1/H

UART

TI/RI

0023H

ES0

PS0/H

TF2, EXF2

003BH

ET2

PT2/H

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