S25FL256SDPNFVC datasheet(47/149 Pages) CYPRESS

47 / 149 page

Document Number: 001-98283 Rev. *M

Page 46 of 148

S25FL128S/S25FL256S

Note

: These are condensed tables that use a couple of sectors as references. There are address ranges that are not explicitly listed.

All 256 kB sectors have the pattern XXX0000h-XXXFFFFh.

7.3

ID-CFI Address Space

The RDID command (9Fh) reads information from a separate flash memory address space for device identification (ID) and

Common Flash Interface (CFI) information. See Section 11.2 Device ID and Common Flash Interface (ID-CFI) Address Map

on page 124 for the tables defining the contents of the ID-CFI address space. The ID-CFI address space is programmed by Cypress

and read-only for the host system.

7.4

OTP Address Space

Each S25FL128S and S25FL256S memory device has a 1024-byte One Time Program (OTP) address space that is separate from

the main flash array. The OTP area is divided into 32, individually lockable, 32-byte aligned and length regions.

In the 32-byte region starting at address zero:



The 16 lowest address bytes are programmed by Cypress with a 128-bit random number. Only Cypress is able to program these

bytes.



The next 4 higher address bytes (OTP Lock Bytes) are used to provide one bit per OTP region to permanently protect each



region from programming. The bytes are erased when shipped from Cypress. After an OTP region is programmed, it can be

locked to prevent further programming, by programming the related protection bit in the OTP Lock Bytes.



The next higher 12 bytes of the lowest address region are Reserved for Future Use (RFU). The bits in these RFU bytes may be

programmed by the host system but it must be understood that a future device may use those bits for protection of a larger OTP

space. The bytes are erased when shipped from Cypress.

The remaining regions are erased when shipped from Cypress, and are available for programming of additional permanent data.

Refer to Figure 42 on page 47 for a pictorial representation of the OTP memory space.

The OTP memory space is intended for increased system security. OTP values, such as the random number programmed by

Cypress, can be used to “mate” a flash component with the system CPU/ASIC to prevent device substitution.

The configuration register FREEZE (CR1[0]) bit protects the entire OTP memory space from programming when set to 1. This allows

trusted boot code to control programming of OTP regions then set the FREEZE bit to prevent further OTP memory space

programming during the remainder of normal power-on system operation.

Table 21. S25FL128S Sector and Memory Address Map, Uniform 256-kbyte Sectors

Sector Size (kbyte) Sector Count

Sector Range

Address Range (Byte Address)

Notes

256

SA00

0000000h-003FFFFh

Sector Starting Address

—

Sector Ending Address

SA63

0FC0000h-0FFFFFFh

S25FL256SDPNFVC Datasheet(PDF) 47 Page - Cypress Semiconductor

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