S25FL256SDPNFVC datasheet(82/149 Pages) CYPRESS

Part #	S25FL256SDPNFVC

Description	128 Mbit (16 Mbyte)/256 Mbit (32 Mbyte) 128 Mbit (16 Mbyte)/256 Mbit (32 Mbyte)

PDF	149 Pages

Scroll/Zoom	100%

Manufacturer	CYPRESS [Cypress Semiconductor]

Direct Link	http://www.cypress.com

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82 / 149 page

Document Number: 001-98283 Rev. *M

Page 81 of 148

S25FL128S/S25FL256S

Figure 56. AutoBoot Sequence (CR1[1]=1)

9.3.13 AutoBoot Register Read (ABRD 14h)

The AutoBoot Register Read command is shifted into SI. Then the 32-bit AutoBoot Register is shifted out on SO, least significant

byte first, most significant bit of each byte first. It is possible to read the AutoBoot Register continuously by providing multiples of 32

clock cycles. If the QUAD bit CR1[1] is cleared to 0, the maximum operating clock frequency for ABRD command is 133 MHz. If the

QUAD bit CR1[1] is set to 1, the maximum operating clock frequency for ABRD command is 104 MHz.

Figure 57. AutoBoot Register Read (ABRD) Command

-n+2

n+1

n+7

n+6

n+5

n+4

Wait State

tWS

n+9

n+8

SCK

IO0

IO1

High Impedance

DATA OUT 1

CS#

n+3

040

High Impedance

6262

High Impedance

IO2

7373

High Impedance

MSB

IO3

210

Instruction

SCK

High Impedance

MSB

AutoBoot Register

MSB

CS#

MSB

S25FL256SDPNFVC Datasheet(PDF) 82 Page - Cypress Semiconductor

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