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S25FL256SDPNFVC Datasheet(PDF) 57 Page - Cypress Semiconductor

Part # S25FL256SDPNFVC
Description  128 Mbit (16 Mbyte)/256 Mbit (32 Mbyte) 128 Mbit (16 Mbyte)/256 Mbit (32 Mbyte)
PDF  149 Pages
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

S25FL256SDPNFVC Datasheet(HTML) 57 Page - Cypress Semiconductor

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Document Number: 001-98283 Rev. *M
Page 56 of 148
S25FL128S/S25FL256S
7.5.9
PPB Lock Register (PPBL)
Related Commands: PPB Lock Read (PLBRD A7h, PLBWR A6h)
7.5.10 PPB Access Register (PPBAR)
Related Commands: PPB Read (PPBRD E2h)
7.5.11 DYB Access Register (DYBAR)
Related Commands: DYB Read (DYBRD E0h) and DYB Program (DYBP E1h).
7.5.12 SPI DDR Data Learning Registers
Related Commands: Program NVDLR (PNVDLR 43h), Write VDLR (WVDLR 4Ah), Data Learning Pattern Read (DLPRD 41h).
The Data Learning Pattern (DLP) resides in an 8-bit Non-Volatile Data Learning Register (NVDLR) as well as an 8-bit Volatile Data
Learning Register (VDLR). When shipped from Cypress, the NVDLR value is 00h. Once programmed, the NVDLR cannot be
reprogrammed or erased; a copy of the data pattern in the NVDLR will also be written to the VDLR. The VDLR can be written to at
any time, but on reset or power cycles the data pattern will revert back to what is in the NVDLR. During the learning phase described
in the SPI DDR modes, the DLP will come from the VDLR. Each IO will output the same DLP value for every clock edge. For
example, if the DLP is 34h (or binary 00110100) then during the first clock edge all IO’s will output 0; subsequently, the 2nd clock
edge all I/O’s will output 0, the 3rd will output 1, etc.
When the VDLR value is 00h, no preamble data pattern is presented during the dummy phase in the DDR commands.
Table 36. PPB Lock Register (PPBL)
Bits
Field Name
Function
Type
Default State
Description
7 to 1
RFU
Reserved
Volatile
00h
Reserved for Future Use
0
PPBLOCK Protect PPB Array
Volatile
Persistent Protection Mode = 1
Password Protection Mode = 0
0 = PPB array protected until next power
cycle or hardware reset
1 = PPB array may be programmed or
erased.
Table 37. PPB Access Register (PPBAR)
Bits
Field Name
Function
Type
Default
State
Description
7 to 0
PPB
Read or Program
per sector PPB
Non-volatile
FFh
00h = PPB for the sector addressed by the PPBRD or
PPBP command is programmed to 0, protecting that
sector from program or erase operations.
FFh = PPB for the sector addressed by the PPBRD or
PPBP command is erased to 1, not protecting that
sector from program or erase operations.
Table 38. DYB Access Register (DYBAR)
Bits
Field Name
Function
Type
Default State
Description
7 to 0
DYB
Read or Write
per sector DYB
Volatile
FFh
00h = DYB for the sector addressed by the DYBRD or DYBP
command is cleared to 0, protecting that sector from program or
erase operations.
FFh = DYB for the sector addressed by the DYBRD or DYBP
command is set to 1, not protecting that sector from program or
erase operations.



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