S25FL256SDPNFVC datasheet(20/149 Pages) CYPRESS

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Document Number: 001-98283 Rev. *M

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S25FL128S/S25FL256S

3.3.1

Power-Off

When the core supply voltage is at or below the VCC (low) voltage, the device is considered to be powered off. The device does not

react to external signals, and is prevented from performing any program or erase operation.

3.3.2

Low Power Hardware Data Protection

When VCC is less than VCC (cut-off) the memory device will ignore commands to ensure that program and erase operations can not

start when the core supply voltage is out of the operating range.

3.3.3

Power-On (Cold) Reset

When the core voltage supply remains at or below the VCC (low) voltage for  tPD time, then rises to  VCC (Minimum) the device will

begin its Power-On Reset (POR) process. POR continues until the end of tPU. During tPU the device does not react to external input

signals nor drive any outputs. Following the end of tPU the device transitions to the Interface Standby state and can accept

commands. For additional information on POR see Section 5.3.1 Power-On (Cold) Reset on page 29.

3.3.4

Hardware (Warm) Reset

Some of the device package options provide a RESET# input. When RESET# is driven low for tRP time the device starts the

hardware reset process. The process continues for tRPH time. Following the end of both tRPH and the reset hold time following the

rise of RESET# (tRH) the device transitions to the Interface Standby state and can accept commands. For additional information on

hardware reset see Section 28 POR followed by Hardware Reset on page 29.

3.3.5

Interface Standby

When CS# is high the SPI interface is in standby state. Inputs other than RESET# are ignored. The interface waits for the beginning

of a new command. The next interface state is Instruction Cycle when CS# goes low to begin a new command.

While in interface standby state the memory device draws standby current (ISB) if no embedded algorithm is in progress. If an

embedded algorithm is in progress, the related current is drawn until the end of the algorithm when the entire device returns to

standby current draw.

3.3.6

Instruction Cycle

When the host drives the MSB of an instruction and CS# goes low, on the next rising edge of SCK the device captures the MSB of

the instruction that begins the new command. On each following rising edge of SCK the device captures the next lower significance

bit of the 8-bit instruction. The host keeps RESET# high, CS# low, HOLD# high, and drives Write Protect (WP#) signal as needed for

the instruction. However, WP# is only relevant during instruction cycles of a WRR command and is otherwise ignored.

Each instruction selects the address space that is operated on and the transfer format used during the remainder of the command.

The transfer format may be Single, Dual output, Quad output, Dual I/O, Quad I/O, DDR Single I/O, DDR Dual I/O, or DDR Quad I/O.

The expected next interface state depends on the instruction received.

Some commands are stand alone, needing no address or data transfer to or from the memory. The host returns CS# high after the

rising edge of SCK for the eighth bit of the instruction in such commands. The next interface state in this case is Interface Standby.

3.3.7

Hold

When Quad mode is not enabled (CR[1]=0) the HOLD# / IO3 signal is used as the HOLD# input. The host keeps RESET# high,

HOLD# low, SCK may be at a valid level or continue toggling, and CS# is low. When HOLD# is low a command is paused, as though

SCK were held low. SI / IO0 and SO / IO1 ignore the input level when acting as inputs and are high impedance when acting as

outputs during hold state. Whether these signals are input or output depends on the command and the point in the command

sequence when HOLD# is asserted low.

When HOLD# returns high the next state is the same state the interface was in just before HOLD# was asserted low.

When Quad mode is enabled the HOLD# / IO3 signal is used as IO3.

During DDR commands the HOLD# and WP# inputs are ignored.

S25FL256SDPNFVC Datasheet(PDF) 20 Page - Cypress Semiconductor

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