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S25FL256SDPNFVC Datasheet(PDF) 19 Page - Cypress Semiconductor |
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S25FL256SDPNFVC Datasheet(HTML) 19 Page - Cypress Semiconductor |
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19 / 149 page  Document Number: 001-98283 Rev. *M Page 18 of 148 S25FL128S/S25FL256S 3.3 Interface States This section describes the input and output signal levels as related to the SPI interface behavior. Legend Z = No driver - floating signal HL = Host driving VIL HH = Host driving VIH HV = Either HL or HH X = HL or HH or Z HT = Toggling between HL and HH ML = Memory driving VIL MH = Memory driving VIH MV = Either ML or MH Table 3. Interface States Summary Interface State VCC VIO RESET# SCK CS# HOLD# / IO3 WP# / IO2 SO / IO1 SI / IO0 Power-Off < VCC (low) VCC XX X X XZ X Low Power Hardware Data Protection <VCC (cut-off) VCC XX X X XZ X Power-On (Cold) Reset ≥ VCC (min) ≥ VIO (min) ≤ VCC XX X X XZ X Hardware (Warm) Reset ≥ VCC (min) ≥ VIO (min) ≤ VCC HL X X X X Z X Interface Standby ≥ VCC (min) ≥ VIO (min) ≤ VCC HH X HH X X Z X Instruction Cycle ≥ VCC (min) ≥ VIO (min) ≤ VCC HH HT HL HH HV Z HV Hold Cycle ≥ VCC (min) ≥ VIO (min) ≤ VCC HH HV or HT HL HL X X X Single Input Cycle Host to Memory Transfer ≥ VCC (min) ≥ VIO (min) ≤ VCC HH HT HL HH X Z HV Single Latency (Dummy) Cycle ≥ VCC (min) ≥ VIO (min) ≤ VCC HH HT HL HH X Z X Single Output Cycle Memory to Host Transfer ≥ VCC (min) ≥ VIO (min) ≤ VCC HH HT HL HH X MV X Dual Input Cycle Host to Memory Transfer ≥ VCC (min) ≥ VIO (min) ≤ VCC HH HT HL HH X HV HV Dual Latency (Dummy) Cycle ≥ VCC (min) ≥ VIO (min) ≤ VCC HH HT HL HH X X X Dual Output Cycle Memory to Host Transfer ≥ VCC (min) ≥ VIO (min) ≤ VCC HH HT HL HH X MV MV QPP Address Input Cycle Host to Memory Transfer ≥ VCC (min) ≥ VIO (min) ≤ VCC HH HT HL X X X HV Quad Input Cycle Host to Memory Transfer ≥ VCC (min) ≥ VIO (min) ≤ VCC HH HT HL HV HV HV HV Quad Latency (Dummy) Cycle ≥ VCC (min) ≥ VIO (min) ≤ VCC HH HT HL X X X X Quad Output Cycle Memory to Host Transfer ≥ VCC (min) ≥ VIO (min) ≤ VCC HH HT HL MV MV MV MV DDR Single Input Cycle Host to Memory Transfer ≥ VCC (min) ≥ VIO (min) ≤ VCC HH HT HL X X X HV DDR Dual Input Cycle Host to Memory Transfer ≥ VCC (min) ≥ VIO (min) ≤ VCC HH HT HL X X HV HV DDR Quad Input Cycle Host to Memory Transfer ≥ VCC (min) ≥ VIO (min) ≤ VCC HH HT HL HV HV HV HV DDR Latency (Dummy) Cycle ≥ VCC (min) ≥ VIO (min) ≤ VCC HH HT HL MV or Z MV or Z MV or Z MV or Z DDR Single Output Cycle Memory to Host Transfer ≥ VCC (min) ≥ VIO (min) ≤ VCC HH HT HL Z Z MV X DDR Dual Output Cycle Memory to Host Transfer ≥ VCC (min) ≥ VIO (min) ≤ VCC HH HT HL Z Z MV MV DDR Quad Output Cycle Memory to Host Transfer ≥ VCC (min) ≥ VIO (min) ≤ VCC HH HT HL MV MV MV MV |
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