S25FL256SDPNFVC datasheet(9/149 Pages) CYPRESS

9 / 149 page

Document Number: 001-98283 Rev. *M

Page 8 of 148

S25FL128S/S25FL256S

Hardware Interface

Serial Peripheral Interface with Multiple Input / Output (SPI-MIO)

Many memory devices connect to their host system with separate parallel control, address, and data signals that require a large

number of signal connections and larger package size. The large number of connections increase power consumption due to so

many signals switching and the larger package increases cost.

The S25FL128S and S25FL256S devices reduce the number of signals for connection to the host system by serially transferring all

control, address, and data information over 4 to 6 signals. This reduces the cost of the memory package, reduces signal switching

power, and either reduces the host connection count or frees host connectors for use in providing other features.

The S25FL128S and S25FL256S devices use the industry standard single bit Serial Peripheral Interface (SPI) and also supports

optional extension commands for two bit (Dual) and four bit (Quad) wide serial transfers. This multiple width interface is called SPI

Multi-I/O or SPI-MIO.

Signal Descriptions

2.1

Input/Output Summary

Table 2. Signal List

Signal

Name

Type

Description

RESET#

Input

Hardware Reset:

Low = device resets and returns to standby state, ready to receive a command. The

signal has an internal pull-up resistor and may be left unconnected in the host system if not used.

SCK

Input

Serial Clock

CS#

Input

Chip Select

SI / IO0

I/O

Serial Input

for single bit data commands or IO0 for Dual or Quad commands.

SO / IO1

I/O

Serial Output

for single bit data commands. IO1 for Dual or Quad commands.

WP# / IO2

I/O

Write Protect

when not in Quad mode. IO2 in Quad mode. The signal has an internal pull-up resistor

and may be left unconnected in the host system if not used for Quad commands.

HOLD# /

IO3

I/O

Hold

(pause) serial transfer in single bit or Dual data commands. IO3 in Quad-I/O mode. The signal

has an internal pull-up resistor and may be left unconnected in the host system if not used for Quad

commands.

VCC

Supply

Core Power Supply.

VIO

Supply

Versatile I/O Power Supply.

VSS

Supply

Ground.

Unused

Not Connected.

No device internal signal is connected to the package connector nor is there any

future plan to use the connector for a signal. The connection may safely be used for routing space for

a signal on a Printed Circuit Board (PCB). However, any signal connected to an NC must not have

voltage levels higher than VIO.

RFU

Reserved

Reserved for Future Use.

No device internal signal is currently connected to the package connector

but there is potential future use of the connector for a signal. It is recommended to not use RFU

connectors for PCB routing channels so that the PCB may take advantage of future enhanced features

in compatible footprint devices.

DNU

Reserved

Do Not Use.

A device internal signal may be connected to the package connector. The connection

may be used by Cypress for test or other purposes and is not intended for connection to any host

system signal. Any DNU signal related function will be inactive when the signal is at VIL. The signal has

an internal pull-down resistor and may be left unconnected in the host system or may be tied to VSS.

Do not use these connections for PCB signal routing channels. Do not connect any host system signal

to this connection.

S25FL256SDPNFVC Datasheet(PDF) 9 Page - Cypress Semiconductor

S25FL256SDPNFVC Datasheet(HTML) 9 Page - Cypress Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL