S25FL256SDPNFVC datasheet(91/149 Pages) CYPRESS

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Document Number: 001-98283 Rev. *M

Page 90 of 148

S25FL128S/S25FL256S

During any operation, if CS# toggles high to low to high for eight cycles (or less) and data input (IO0 and IO1) are not set for a valid

instruction sequence, then the device will be released from Dual I/O Enhanced High Performance Read mode. Note that the four

mode bit cycles are part of the device’s internal circuitry latency time to access the initial address after the last address cycle that is

clocked into IO0 (SI) and IO1 (SO).

It is important that the I/O signals be set to high-impedance at or before the falling edge of the first data out clock. At higher clock

speeds the time available to turn off the host outputs before the memory device begins to drive (bus turn around) is diminished. It is

allowed and may be helpful in preventing I/O signal contention, for the host system to turn off the I/O signal outputs (make them high

impedance) during the last two “don’t care” mode cycles or during any dummy cycles.

Following the latency period the memory content, at the address given, is shifted out two bits at a time through IO0 (SI) and IO1

(SO). Two bits are shifted out at the SCK frequency at the falling edge of SCK signal.

The address can start at any byte location of the memory array. The address is automatically incremented to the next higher address

in sequential order after each byte of data is shifted out. The entire memory can therefore be read out with one single read

instruction and address 000000h provided. When the highest address is reached, the address counter will wrap around and roll back

to 000000h, allowing the read sequence to be continued indefinitely.

CS# should not be driven high during mode or dummy bits as this may make the mode bits indeterminate.

Figure 62. Dual I/O Read Command Sequence (3-byte Address, BBh [ExtAdd=0], HPLC=00b)

Figure 9.16 Dual I/O Read Command Sequence (4-byte Address, BBh [ExtAdd=1], HPLC=10b)

Figure 9.17 Dual I/O Read Command Sequence (4-byte Address, BCh or BBh [ExtAdd=1], EHPLC=10b)

CS#

SCK

IO0

IO1

Phase

22 20 18

23 21 19

Instruction

Address

4 Dummy

Data 1

Data 2

CS#

SCK

IO0

IO1

Phase

30 28 26

31 29 27

Instruction

Address

6 Dummy

Data 1

Data 2

Instruction

32 Bit Address

Mode

Dummy

Data 1

Data 2

8 cycles

16 cycles

4 cycles

2 cycles

4 cycles

CS#

SCK

IO0

IO1

S25FL256SDPNFVC Datasheet(PDF) 91 Page - Cypress Semiconductor

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