S25FL256SDPNFVC datasheet(95/149 Pages) CYPRESS

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Document Number: 001-98283 Rev. *M

Page 94 of 148

S25FL128S/S25FL256S

When the EHPLC table is used, address jumps can be done without the need for additional DDR Fast Read instructions. This is

controlled through the setting of the Mode bits (after the address sequence, as shown in Figure 9.22 on page 94 and Figure 9.24

on page 95. This added feature removes the need for the eight bit SDR instruction sequence to reduce initial access time (improves

XIP performance). The Mode bits control the length of the next DDR Fast Read operation through the inclusion or exclusion of the

first byte instruction code. If the upper nibble (IO[7:4]) and lower nibble (IO[3:0]) of the Mode bits are complementary (i.e. 5h and Ah)

then the next address can be entered (after CS# is raised high and then asserted low) without requiring the 0Dh or 0Eh instruction,

as shown in Figure 9.23 and Figure 9.25, thus, eliminating eight cycles from the command sequence. The following sequences will

release the device from this continuous DDR Fast Read mode; after which, the device can accept standard SPI commands:

1. During the DDR Fast Read Command Sequence, if the Mode bits are not complementary the next time CS# is raised high

the device will be released from the continuous DDR Fast Read mode.

2. During any operation, if CS# toggles high to low to high for eight cycles (or less) and data input (SI) are not set for a valid

instruction sequence, then the device will be released from DDR Fast Read mode.

CS# should not be driven high during mode or dummy bits as this may make the mode bits indeterminate.

The HOLD function is not valid during any part of a Fast DDR Command.

Although the data learning pattern (DLP) is programmable, the following example shows example of the DLP of 34h. The DLP 34h

(or 00110100) will be driven on each of the active outputs (i.e. all four IOs on a x4 device, both IOs on a x2 device and the single SO

output on a x1 device). This pattern was chosen to cover both DC and AC data transition scenarios. The two DC transition scenarios

include data low for a long period of time (two half clocks) followed by a high going transition (001) and the complementary low going

transition (110). The two AC transition scenarios include data low for a short period of time (one half clock) followed by a high going

transition (101) and the complementary low going transition (010). The DC transitions will typically occur with a starting point closer

to the supply rail than the AC transitions that may not have fully settled to their steady state (DC) levels. In many cases the DC

transitions will bound the beginning of the data valid period and the AC transitions will bound the ending of the data valid period.

These transitions will allow the host controller to identify the beginning and ending of the valid data eye. Once the data eye has been

characterized the optimal data capture point can be chosen. See Section 7.5.12 SPI DDR Data Learning Registers on page 56 for

more details.

Figure 9.22 DDR Fast Read Initial Access (3-byte Address, 0Dh [ExtAdd=0, EHPLC=11b])

Figure 9.23 Continuous DDR Fast Read Subsequent Access (3-byte Address [ExtAdd=0, EHPLC=11b])

Instruction

24 Bit Address

Mode

Dummy

per data

8 cycles

12 cycles

4 cycles

1 cyc

4 cycles

CS#

SCK

IO0

IO1

24 Bit Address

Mode

Dummy

per data

12 cycles

4 cycles

1 cyc

4 cycles

CS#

SCK

IO0

IO1

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