S25FL256SDPNFVC datasheet(64/149 Pages) CYPRESS

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Document Number: 001-98283 Rev. *M

Page 63 of 148

S25FL128S/S25FL256S

8.4.6

Persistent Protection Mode

The Persistent Protection method sets the PPB Lock bit to 1 during POR or Hardware Reset so that the PPB bits are unprotected by

a device hardware reset. Software reset does not affect the PPB Lock bit. The PLBWR command can clear the PPB Lock bit to 0 to

protect the PPB. There is no command to set the PPB Lock bit therefore the PPB Lock bit will remain at 0 until the next power-off or

hardware reset.

8.4.7

Password Protection Mode

Password Protection Mode allows an even higher level of security than the Persistent Sector Protection Mode, by requiring a 64-bit

password for unlocking the PPB Lock bit. In addition to this password requirement, after power up and hardware reset, the PPB Lock

bit is cleared to 0 to ensure protection at power-up. Successful execution of the Password Unlock command by entering the entire

password clears the PPB Lock bit, allowing for sector PPB modifications.

Password Protection Notes:



Once the Password is programmed and verified, the Password Mode (ASPR[2]=0) must be set in order to prevent reading the

password.



The Password Program Command is only capable of programming ‘0’s. Programming a 1 after a cell is programmed as a 0

results in the cell left as a 0 with no programming error set.



The password is all 1’s when shipped from Cypress. It is located in its own memory space and is accessible through the use of the

Password Program and Password Read commands.



All 64-bit password combinations are valid as a password.



The Password Mode, once programmed, prevents reading the 64-bit password and further password programming. All further

program and read commands to the password region are disabled and these commands are ignored. There is no means to verify

what the password is after the Password Mode Lock Bit is selected. Password verification is only allowed before selecting the

Password Protection mode.



The Protection Mode Lock Bits are not erasable.



The exact password must be entered in order for the unlocking function to occur. If the password unlock command provided

password does not match the hidden internal password, the unlock operation fails in the same manner as a programming

operation on a protected sector. The P_ERR bit is set to one and the WIP Bit remains set. In this case it is a failure to change the

state of the PPB Lock bit because it is still protected by the lack of a valid password.



The Password Unlock command cannot be accepted any faster than once every 100 µs ± 20 µs. This makes it take an

unreasonably long time (58 million years) for a hacker to run through all the 64-bit combinations in an attempt to correctly match a

password. The Read Status Register 1 command may be used to read the WIP bit to determine when the device has completed

the password unlock command or is ready to accept a new password command. When a valid password is provided the password

unlock command does not insert the 100 µs delay before returning the WIP bit to zero.



If the password is lost after selecting the Password Mode, there is no way to set the PPB Lock bit.



ECC status may only be read from sectors that are readable. In read protection mode the addresses are forced to the boot sector

address. ECC status is shown in that sector while read protection mode is active.

Table 43. Sector Protection States

Protection Bit Values

Sector State

PPB Lock

PPB

DYB

Unprotected – PPB and DYB are changeable

Protected – PPB and DYB are changeable

Unprotected – PPB not changeable, DYB is changeable

Protected – PPB not changeable, DYB is changeable

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