S25FL256SDPNFVC datasheet(78/149 Pages) CYPRESS

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Document Number: 001-98283 Rev. *M

Page 77 of 148

S25FL128S/S25FL256S

Figure 50. Write Registers (WRR) Command Sequence – 16 data bits

The Write Registers (WRR) command allows the user to change the values of the Block Protect (BP2, BP1, and BP0) bits to define

the size of the area that is to be treated as read-only. The Write Registers (WRR) command also allows the user to set the Status

Register Write Disable (SRWD) bit to a 1 or a 0. The Status Register Write Disable (SRWD) bit and Write Protect (WP#) signal allow

the BP bits to be hardware protected.

When the Status Register Write Disable (SRWD) bit of the Status Register is a 0 (its initial delivery state), it is possible to write to the

Status Register provided that the Write Enable Latch (WEL) bit has previously been set by a Write Enable (WREN) command,

regardless of the whether Write Protect (WP#) signal is driven to the logic high or logic low state.

When the Status Register Write Disable (SRWD) bit of the Status Register is set to a 1, two cases need to be considered, depending

on the state of Write Protect (WP#):



If Write Protect (WP#) signal is driven to the logic high state, it is possible to write to the Status and Configuration Registers

provided that the Write Enable Latch (WEL) bit has previously been set to a 1 by initiating a Write Enable (WREN) command.



If Write Protect (WP#) signal is driven to the logic low state, it is not possible to write to the Status and Configuration Registers

even if the Write Enable Latch (WEL) bit has previously been set to a 1 by a Write Enable (WREN) command. Attempts to write to

the Status and Configuration Registers are rejected, and are not accepted for execution. As a consequence, all the data bytes in

the memory area that are protected by the Block Protect (BP2, BP1, BP0) bits of the Status Register, are also hardware protected

by WP#.

The WP# hardware protection can be provided:



by setting the Status Register Write Disable (SRWD) bit after driving Write Protect (WP#) signal to the logic low state;



or by driving Write Protect (WP#) signal to the logic low state after setting the Status Register Write Disable (SRWD) bit to a 1.

The only way to release the hardware protection is to pull the Write Protect (WP#) signal to the logic high state. If WP# is

permanently tied high, hardware protection of the BP bits can never be activated.

Notes:

1. The Status Register originally shows 00h when the device is first shipped from Cypress to the customer.

2. Hardware protection is disabled when Quad Mode is enabled (QUAD bit = 1 in Configuration Register). WP# becomes IO2; therefore, it cannot be utilized.

The WRR command has an alternate function of loading the Bank Address Register if the command immediately follows a BRAC

command. See Section 9.3.6 Bank Register Access (BRAC B9h) on page 75.

Table 48. Block Protection Modes

WP#

SRWD Bit

Mode

Write Protection of Registers

Memory Content

Protected Area

Unprotected Area

Software Pro-

tected

Status and Configuration Registers are Writable (if

WREN command has set the WEL bit). The values in

the SRWD, BP2, BP1, and BP0 bits and those in the

Configuration Register can be changed

Protected against Page

Program, Quad Input

Program, Sector

Erase, and Bulk Erase

Ready to accept Page

Program, Quad Input

Program and Sector

Erase commands

Hardware

Protected

Status and Configuration Registers are Hardware

Write Protected. The values in the SRWD, BP2, BP1,

and BP0 bits and those in the Configuration Register

cannot be changed

Protected against Page

Program, Sector

Erase, and Bulk Erase

Ready to accept Page

Program or Erase

commands

IInstruction

Status Register In

SCK

MSB

High Impedance

Configuration Register In

MSB

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