S25FL256SDPNFVC datasheet(67/149 Pages) CYPRESS

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Document Number: 001-98283 Rev. *M

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S25FL128S/S25FL256S

2. For backward compatibility to the 3-byte address instructions, the standard instructions can be used in conjunction with

the EXTADD Bit in the Bank Address Register (BAR[7]). By default BAR[7] is cleared to 0 (following power up and

hardware reset), to enable 3-byte (24-bit) addressing. When set to 1, the legacy commands are changed to require 4

bytes (32 bits) for the address field. The following instructions can be used in conjunction with EXTADD bit to switch from

3 bytes to 4 bytes of address field.

3. For backward compatibility to the 3-byte addressing, the standard instructions can be used in conjunction with the Bank

Address Register:

a. The Bank Address Register is used to switch between 128-Mbit (16-Mbyte) banks of memory, The standard 3-byte

address selects an address within the bank selected by the Bank Address Register.

i. The host system writes the Bank Address Register to access beyond the first 128 Mbits of

memory.

ii. This applies to read, erase, and program commands.

b. The Bank Register provides the high order (4th) byte of address, which is used to address the available memory at

addresses greater than 16 Mbytes.

c. Bank Register bits are volatile.

i. On power up, the default is Bank0 (the lowest address 16 Mbytes).

d. For Read, the device will continuously transfer out data until the end of the array.

i. There is no bank to bank delay.

ii. The Bank Address Register is not updated.

iii. The Bank Address Register value is used only for the initial address of an access.

Instruction Name

Description

Code (Hex)

READ

Read (3-byte Address)

FAST_READ

Read Fast (3-byte Address)

DOR

Read Dual Out (3-byte Address)

QOR

Read Quad Out (3-byte Address)

DIOR

Dual I/O Read (3-byte Address)

QIOR

Quad I/O Read (3-byte Address)

DDRFR

Read DDR Fast (3-byte Address)

DDRDIOR

DDR Dual I/O Read (3-byte Address)

DDRQIOR

DDR Quad I/O Read (3-byte Address)

Page Program (3-byte Address)

QPP

Quad Page Program (3-byte Address)

P4E

Parameter 4-kB Erase (3-byte Address)

Erase 64 / 256 kB (3-byte Address)

Table 44. Bank Address Map

Bank Address Register Bits

Bank

Memory Array Address Range (Hex)

Bit 1

Bit 0

00000000

00FFFFFF

01000000

01FFFFFF

S25FL256SDPNFVC Datasheet(PDF) 67 Page - Cypress Semiconductor

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