S25FL256SDPNFVC datasheet(7/149 Pages) CYPRESS

7 / 149 page

Document Number: 001-98283 Rev. *M

Page 6 of 148

S25FL128S/S25FL256S

1.2.2

Known Differences from Prior Generations

1.2.2.1 Error Reporting

Prior generation FL memories either do not have error status bits or do not set them if program or erase is attempted on a protected

sector. The FL-S family does have error reporting status bits for program and erase operations. These can be set when there is an

internal failure to program or erase or when there is an attempt to program or erase a protected sector. In either case the program or

erase operation did not complete as requested by the command.

1.2.2.2 Secure Silicon Region (OTP)

The size and format (address map) of the One Time Program area is different from prior generations. The method for protecting

each portion of the OTP area is different. For additional details see Section 8.1 Secure Silicon Region (OTP) on page 58.

1.2.2.3 Configuration Register Freeze Bit

The configuration register Freeze bit CR1[0], locks the state of the Block Protection bits as in prior generations. In the FL-S family it

also locks the state of the configuration register TBPARM bit CR1[2], TBPROT bit CR1[5], and the Secure Silicon Region (OTP)

area.

1.2.2.4 Sector Erase Commands

The command for erasing an 8-kbyte area (two 4-kbyte sectors) is not supported.

The command for erasing a 4-kbyte sector is supported only in the 128-Mbit and 256-Mbit density FL-S devices and only for use on

the thirty two 4-kbyte parameter sectors at the top or bottom of the device address space.

The erase command for 64-kbyte sectors are supported for the 128-Mbit and 256-Mbit density FL-S devices when the ordering

option for 4-kbyte parameter sectors with 64-kbyte uniform sectors are used. The 64-kbyte erase command may be applied to erase

a group of sixteen 4-kbyte sectors.

The erase command for a 256-kbyte sector replaces the 64-kbyte erase command when the ordering option for 256-kbyte uniform

sectors is used for the 128-Mbit and 256-Mbit density FL-S devices.

1.2.2.5 Deep Power Down

The Deep Power Down (DPD) function is not supported in FL-S family devices.

The legacy DPD (B9h) command code is instead used to enable legacy SPI memory controllers, that can issue the former DPD

command, to access a new bank address register. The bank address register allows SPI memory controllers that do not support

more than 24 bits of address, the ability to provide higher order address bits for commands, as needed to access the larger address

space of the 256-Mbit density FL-S device. For additional information see Section 7.1.1 Extended Address on page 44.

1.2.2.6 New Features

The FL-S family introduces several new features to SPI category memories:



Extended address for access to higher memory density.



AutoBoot for simpler access to boot code following power up.



Enhanced High Performance read commands using mode bits to eliminate the overhead of SIO instructions when repeating the

same type of read command.



Multiple options for initial read latency (number of dummy cycles) for faster initial access time or higher clock rate read

commands.



DDR read commands for SIO, DIO, and QIO.



Automatic ECC for enhanced data integrity.



Advanced Sector Protection for individually controlling the protection of each sector. This is very similar to the Advanced Sector

Protection feature found in several other Cypress parallel interface NOR memory families.

S25FL256SDPNFVC Datasheet(PDF) 7 Page - Cypress Semiconductor

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