S25FL256SDPNFVC datasheet(83/149 Pages) CYPRESS

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Document Number: 001-98283 Rev. *M

Page 82 of 148

S25FL128S/S25FL256S

9.3.14 AutoBoot Register Write (ABWR 15h)

Before the ABWR command can be accepted, a Write Enable (WREN) command must be issued and decoded by the device, which

sets the Write Enable Latch (WEL) in the Status Register to enable any write operations.

The ABWR command is entered by shifting the instruction and the data bytes on SI, least significant byte first, most significant bit of

each byte first. The ABWR data is 32 bits in length.

The ABWR command has status reported in Status Register-1 as both an erase and a programming operation. An E_ERR or a

P_ERR may be set depending on whether the erase or programming phase of updating the register fails.

CS# must be driven to the logic high state after the 32nd bit of data has been latched. If not, the ABWR command is not executed.

As soon as CS# is driven to the logic high state, the self-timed ABWR operation is initiated. While the ABWR operation is in

progress, Status Register-1 may be read to check the value of the Write-In Progress (WIP) bit. The Write-In Progress (WIP) bit is a

1 during the self-timed ABWR operation, and is a 0. when it is completed. When the ABWR cycle is completed, the Write Enable

Latch (WEL) is set to a 0. The maximum clock frequency for the ABWR command is 133 MHz.

Figure 58. AutoBoot Register Write (ABWR) Command

9.3.15 Program NVDLR (PNVDLR 43h)

Before the Program NVDLR (PNVDLR) command can be accepted by the device, a Write Enable (WREN) command must be

issued and decoded by the device. After the Write Enable (WREN) command has been decoded successfully, the device will set the

Write Enable Latch (WEL) to enable the PNVDLR operation.

The PNVDLR command is entered by shifting the instruction and the data byte on SI.

CS# must be driven to the logic high state after the eighth (8th) bit of data has been latched. If not, the PNVDLR command is not

executed. As soon as CS# is driven to the logic high state, the self-timed PNVDLR operation is initiated. While the PNVDLR

operation is in progress, the Status Register may be read to check the value of the Write-In Progress (WIP) bit. The Write-In

Progress (WIP) bit is a 1 during the self-timed PNVDLR cycle, and is a 0. when it is completed. The PNVDLR operation can report a

program error in the P_ERR bit of the status register. When the PNVDLR operation is completed, the Write Enable Latch (WEL) is

set to a 0 The maximum clock frequency for the PNVDLR command is 133 MHz.

Figure 59. Program NVDLR (PNVDLR) Command Sequence

Instruction

AutoBoot Register

210

SCK

MSB

High Impedance

CS#

MSB

IIn stru ctio n

D a ta L e a rn in g P a tte rn

1 0

1 4

1 3

1 2

1 5

S C K

S I

S O

M S B

H ig h Im p e d a n ce

C S

M S B

1 1

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