LM5177DCPR datasheet(23/60 Pages) TI2

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RRT = 1fsw −20ns ×30.3GΩs

(2)

The RT pin is regulated to 0.75 V by an internal voltage source when the device is in active mode. Therefore, the

switching frequency can be dynamically changed during operation by changing the current flowing through the

resistor. Figure 7-9 and Figure 7-10 show two examples for changing the frequency by the switching the resistor

value or applying a external voltage source through a resistor. It is not recommended to connect any additional

capacitance directly to the RT pin.

Incr ease f(sw)

Figure 7-9. Frequency Hopping Example

Figure 7-10. Dynamic Frequency Changing

Example

7.3.7 Frequency Synchronization

The device features an internal phase looked loop (PLL), which is designed to transition the switching frequency

seamlessly between the frequency set by the RT pin and the external frequency synchronization signal. If no

external frequency is provided, the RT pin sets the center frequency of the PLL. The external synchronization

signal can change the switching frequency ±50%. To ensure low quiescence current, the input buffer of

the SYNC pin is disabled if no valid sync frequency, that is a frequency signal outside the recommended

synchronization range is applied.

If a valid synchronization frequency is applied, the device does not enter uSleep during the PSM pause. The

internal PLL is kept active to quickly re-syncs to the external synchronization signal in case of a increased load

e.g. due to a load step on the output. This behavior improves the transient responds but causes higher quiescent

currents for light load operation because the uSleep is disabled if a synchronization signal is provide to the

SYNC pin.

The synchronization timings are given in Figure 7-12.

VT(SYNC)

OSC

PLL

CORE

LOGIC

SYNC

ACTIVITY

DETECTION

LIMITER

Figure 7-11. Main Oscillator Functional Block Diagram

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LM5177

SNVSBU4F – JUNE 2022 – REVISED JANUARY 2025

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LM5177DCPR Datasheet(PDF) 23 Page - Texas Instruments