LM5177DCPR datasheet(24/60 Pages) TI2

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V(SYNC)

VT+(SYNC)

PLL lock Cycles

VT-(SYNC)

td(Det,Sync)

RT pro gramed fsw

td(Det,Sync)

fsw Synced

RT pro gramed fsw

Figure 7-12. Timing Diagram SYNC Function

The sync pin has a dual function to configure the current limit direction during the initialization phase. If pulled

low during this time the negative current limit is selected. Otherwise the positive current limit is selected.

7.3.8 Voltage Regulation Loop

The LM5177 features an internal error amplifier (EA) to regulate the output voltage. The output voltage gets

sensed on the FB pin through external resistors, which determine the target or nominal output voltage. The

reference for the EA builds the soft-start and analog output voltage tracking pin (SS/ATRK). The COMP pin is the

output of the internal gm-stage and gets connected to the external compensation network. The voltage over the

compensation network is the nominal value for the inner peak current control loop of the device.

Use the following equations to calculate the external components:

External Feedback:

RCOMP = 2π ×fBW

gmea ×RFB,bot +RFB,top

RFB,bot ×10 ×RCS ×CO

1−Dmax

(3)

CCOMP = 1

2π× fCZ ×RCOMP

(4)

CPCOMP =

2π×10× fBW ×RCOMP

(5)

For most applications, TI recommends the following guidelines for bandwidth selection of the compensation.

The hard limit of the bandwidth (f(BW)) is the right half plane zero of the boost operation:

fRHPZ= 12π×VVOUT× 1−Dmax2

Io,max×L

(6)

The maximum recommended bandwidth must be within the following boundaries:

fBW <13×fRHPZ

(7)

fBW < 110× 1−Dmax ×fSW

(8)

The compensation zero (fCZ) must be placed in relation to the dominating pole of the boost.

fCZ=1.5×fpole,boost

(9)

LM5177

SNVSBU4F – JUNE 2022 – REVISED JANUARY 2025

www.ti.com

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