LM5177DCPR datasheet(31/60 Pages) TI2

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As this threshold is referenced to the V(REF) the OVP1 continues its operation even if of tracking features has

changed the Vo target value.

The converter maintains in regulation even the OVP1 threshold triggers.

The OVP1 is disabled during PSM to avoid additional leakage current. The OVP signal gets masked to avoid

that a fault is indicated from this signal during the PSM operation.

This protection is disabled during the soft-start procedure.

Output Over Voltage protection 2 (OVP2)

This feature shall avoid any damage to the device in case the external feedback pin is not working properly i.e. is

shorted to GND

If the output voltage threshold VT+(OVP2) is reached on the VOUT-pin the buck-boost core logic disables the

converter power stage and enters a high impedance state at the switch nodes. If the output voltage falls back

under this threshold the convert operation is resumed.

Input Voltage Protection (IVP)

The input over voltage protection is part of the converter core modulation scheme. The IVP avoids any damage

to the device in case the current flows from the output to the input and the input source can not sink current e.g.

there is a diode in the supply path. If the converter forced PWM mode is active the current can go negative until

the sink current limit. Once the input voltage threshold VT+(IVP) is reach on the VIN-pin the protection disables

the forced PWM mode and only allows current to flow from VIN to VOUT. After the input voltage drops under the

input voltage protection threshold, the fPWM mode activates again.

Power Good

The device features a power good detection. The FB pin voltages gets contentiously monitors. If the sensed

voltage drops below the PG falling threshold the signal is pulling low the nFLT pin.

This protection is disabled during the soft-start procedure.

Boot-strap Under Voltage Protection

The high side supply voltage for the gate driver are monitored by an UVLO comparator (BST_UV). This

comparator monitors the differential voltage between SWx pin and HBx pin. If the measured voltage drops

below VTH-(BST_UV) the converter stops operation

Boot-strap Over Voltage Clamp

To protect the internal gate driver circuit the external FET gates and the internal circuit features an over voltage

clamp. If the voltage goes above VTH(BST_OV) the linear regulator sinks a current from HBx pin to SWx-pin as

long as the voltage is above the threshold.

7.3.16 Device Configuration Pin

The resistor selection on the CFG pin is read and latched during the power-up sequence of the device. The

selection cannot be changed until the voltage on the EN or UVLO reaches the falling threshold or VCC voltage

drops below the VCCT-(UVLO) threshold. Table 7-1 shows the possible device configurations versus the different

resistor values on the CFG pin.

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LM5177

SNVSBU4F – JUNE 2022 – REVISED JANUARY 2025

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LM5177DCPR Datasheet(PDF) 31 Page - Texas Instruments