LM5177DCPR datasheet(41/60 Pages) TI2

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RSLOPE= L1RCS×50 MVAs

(24)

This slope compensation results in “dead-beat” operation, in which the current loop disturbances die out in one

switching cycle. Theoretically, a current mode loop is stable with half the “dead-beat” slope (considered already

in the calculated slope resistor value in Equation 24). A smaller slope resistor results in larger slope signal,

which is better for noise immunity in the transition region (VIN is approximately equal to VOUT). A larger slope

signal, however, restricts the achievable input voltage range for a given output voltage, switching frequency, and

inductor. For this design, RSLOPE = 69.8 kΩ is selected for better transition region behavior while still providing

the required VIN range. This selection of slope resistor, inductor, switching frequency, and inductor satisfies

guidelines given by Equation 12 and Equation 13.

8.2.2.6 Output Capacitor

In boost mode, the output capacitor conducts high ripple current. The output capacitor RMS ripple current is

given by Equation 25 where the minimum VIN corresponds to the maximum capacitor current.

ICOUTRMS = IOUT× VOUTVIN−1

(25)

In this example, the maximum output ripple RMS current is ICOUT(RMS) = 10.3 A. A 2-mΩ output capacitor ESR

causes an output ripple voltage of 42.6 mV as given by:

∆VRIPPLEESR = IOUT×VOUT

VINMIN ×ESR

(26)

A 130-µF output capacitor causes a capacitive ripple voltage of 96 mV as given by:

∆VRIPPLECOUT = IOUT× 1−VINMINVOUT

COUT× fSW

(27)

Typically, a combination of ceramic and bulk capacitors is needed to provide low ESR and high ripple current

capacity. The complete schematic in Figure 8-1 shows a good starting point for COUT for typical applications.

8.2.2.7 Input Capacitor

In buck mode, the input capacitor supplies high ripple current. The RMS current in the input capacitor is given

by:

ICINRMS = IOUT× D× 1−D

(28)

The maximum RMS current occurs at D = 0.5, which gives ICIN(RMS) = IOUT / 2 = 4.0 A. A combination of ceramic

and bulk capacitors must be used to provide a short path for high di/dt current and to reduce the input voltage

ripple. The complete schematic in Figure 8-1 shows a good starting point for CIN for typical applications.

8.2.2.8 UVLO Divider

The UVLO resistor divider must be designed for turn-on below 5.5 V. Selecting RUVLO,top = 75 kΩ gives a UVLO

hysteresis of 0.375 V based on Equation 29. The lower UVLO resistor is selected using:

VVIN,IT+,UVLO =VIT+ UVLO × 1+RUVLO,top

RUVLO,bot + RUVLO,top ×I(UVLO,hyst)

(29)

A standard value of 20.5 kΩ is selected for RUVLO,bot.

When programming the UVLO threshold for lower input voltage operation, it is important to choose MOSFETs

with gate (Miller) plateau voltage lower than the minimum VIN.

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LM5177

SNVSBU4F – JUNE 2022 – REVISED JANUARY 2025

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