LM5177DCPR datasheet(49/60 Pages) TI2

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10 Layout

A proper PCB design and layout is important in high-current, fast-switching circuits (with high current and voltage

slew rates) to achieve a robust and reliable design. As expected, certain topics must be considered for the

design of the PCB layout for the LM5177.

10.1 Layout Guidelines

10.1.1 Power Stage Layout

Input capacitors, output capacitors, and MOSFETs are the constituent components of the power stage of the

buck-boost regulator and are typically placed on the top side of the PCB. The benefits of convective heat transfer

are maximized when leveraging any system-level airflow. In a two-sided PCB layout, small-signal components

are typically placed on the bottom side. Insert at least one inner plane, connected to ground, to shield, and

isolate the small-signal traces from noisy power traces.

The DC/DC regulator has several high-current loops. Minimize the area of these loops to suppress generated

switching noise and optimize switching performance.

• The most important loop areas to minimize are the path from the input capacitors through the buck high-side

and low-side MOSFETs, and back to the ground connection of the input capacitor and the path from the

output capacitors through the boost high-side and low-side MOSFETs, and back to the ground connection

of the output capacitor. Connect the negative terminal of the capacitor close to the source of the low-side

MOSFETs (at ground). Similarly, connect the positive terminal of the capacitor or capacitors close to the drain

of the high-side MOSFETs of both loops.

• In addition to these recommendations, follow any layout considerations of the MOSFETs as recommended by

the MOSFET manufacturer, including pad geometry and solder paste stencil design.

10.1.2 Gate Driver Layout

The LM5177 high-side and low-side gate drivers incorporate short propagation delays, frequency depended

dead-time control, and low-impedance output stages capable of delivering large peak currents with very fast rise

and fall times to facilitate rapid turn-on and turn-off transitions of the external power MOSFETs. Very high di/dt

can cause unacceptable ringing if the trace lengths are not well controlled. Minimization of stray or parasitic

gate loop inductance is key to optimizing gate drive switching performance, whether it be series gate inductance

that resonates with MOSFET gate capacitance or common source inductance (common to gate and power

loops) that provides a negative feedback component opposing the gate drive command, and thereby increasing

MOSFET switching times.

Connections from the gate driver outputs, HO1 and HO2, to the respective gates of the high-side MOSFETs

must be as short as possible to reduce series parasitic inductance. Route HO1 and HO2 and SW1 and

SW2 gate traces as a differential pair from the device pin to the high-side MOSFET, taking advantage of flux

cancellation by reducing the loop area.

Connections from gate driver outputs, LO1 and LO2, to the respective gates of the low-side MOSFETs must

be as short as possible to reduce series parasitic inductance. Route LO1 and LO2, and PGND traces as a

differential pair from the device pin to the low-side MOSFET, taking advantage of flux cancellation by reducing

the loop area.

Minimize the current loop path from the VCC, HB1, and HB2 pins through their respective capacitors as these

provide the high instantaneous current.

10.1.3 Controller Layout

With the provision to locate the controller as close as possible to the power MOSFETs to minimize gate driver

trace runs, the components related to the analog and feedback signals as well as current sensing are considered

in the following:

• Separate power and signal traces, and use a ground plane to provide noise shielding.

• Place all sensitive analog traces and components related to COMP, FB, SLOPE, SS/ATRK, and RT away

from high-voltage switching nodes such as the following to avoid mutual coupling:

– SW1

www.ti.com

LM5177

SNVSBU4F – JUNE 2022 – REVISED JANUARY 2025

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