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MCPF1412M06 Datasheet(PDF) 7 Page - Microchip Technology |
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MCPF1412M06 Datasheet(HTML) 7 Page - Microchip Technology |
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7 / 63 page ![]() MCPF1412M06 Functional Description Data Sheet © 2025 Microchip Technology Inc. and its subsidiaries DS60001885C - 7 • +9 – 7.15 kΩ • +10 – 7.87 kΩ • +11 – 8.66 kΩ • +12 – 9.31 kΩ • +13 – 10.2 kΩ • +14 – 11 kΩ • +15 – 12.1 kΩ Note: Avoid using the 7-bit address 0x0C, as it corresponds to the Alert Response Address in the SMBus™ protocol. 2.5. Soft Start and Target Output Voltage The MCPF1412M06 features an internal digital soft start circuit designed to manage the output voltage rise-time and limit current surges during start-up. When VCC surpasses its start threshold (VCC_UVLO(START)), the MCPF1412M06 exits reset mode, initiating the loading of non-volatile memory contents into working registers and calculating the address offset as previously described. After initialization, the internal soft start ramps up towards the set reference voltage at a rate specified by the TON_RISE registers (associated with the TON_RISE command), provided the following conditions are met: 1. A valid enable signal is detected, as defined by the Enable pin, Operation register, ON_OFF_CONFIG register, input voltage PVIN, and PVIN UVLO threshold corresponding to the VIN_ON registers. 2. The internal pre-charge circuit ensures balanced PVIN/2 voltages across all FETs when the device begins switching. During initial start-up, the MCPF1412M06 operates with minimal high-drive (HDrv) pulses until the output voltage increases (refer to Switching frequency and minimum values for ON-time, OFF- time). The ON time is increased until VOUT reaches the target value set by the VOUT_COMMAND registers. For optimal start-up performance, it is recommended to use a 100Ω resistor connected in parallel with the output capacitors (COUT). A minimum wait time of 600Ω × COUT is advised between successive power or Enable cycling operations. For instance, with a 100Ω resistor across four 47 μF output capacitors, a new Enable assertion should not occur until at least 78 ms (allowing the reduction of capacitance at a bias of 1V - see Design Example) after disabling the MCPF1412M06. |
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