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MCPF1412M06 Datasheet(PDF) 14 Page - Microchip Technology |
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MCPF1412M06 Datasheet(HTML) 14 Page - Microchip Technology |
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14 / 63 page ![]() MCPF1412M06 Functional Description Data Sheet © 2025 Microchip Technology Inc. and its subsidiaries DS60001885C - 14 • Both EN and VCC exceed their thresholds • No faults are present (including overcurrent, overvoltage, and overtemperature) • VOUT is within the target range (monitored continuously to ensure FB is above the PG threshold) With the PGControl bit set to '0' the operation is as shown in Figure 2-9. Figure 2-9. PG Operation With PGControl Bit Set to '0' 85% VOUT 90% VOUT 90% VOUT VOUT PG Int SS 98% of target VOUT During normal operation, the PG signal functions identically to when the PGControl bit is set to '1'. However, at start-up, the PG signal is asserted once FB is within 2% of the target output voltage, rather than when FB surpasses the upper PG threshold. The MCPF1412M06 also includes an additional PMOS in parallel with the NMOS, internally connected to the PG pin (see Block Diagram). This PMOS ensures that the PG signal remains at a logic low level, even if VCC is low and the PG pin is pulled up to an external voltage other than VCC. |
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