FN8724 datasheet(30/34 Pages) RENESAS

30 / 34 page

ISL98608IIH

FN8724 Rev.2.01

Page 30 of 33

Dec 7, 2021

More ground plane area minimizes parasitics and avoids

corruption of the ground reference.

5. Low frequency digital signals should be isolated from any

high frequency signals generated by switching frequency and

harmonics. PCB traces should not cross each other. If they

must cross due to the layout restriction, then they must cross

perpendicularly to reduce the magnetic field interaction.

6. The amount of copper that should be poured (thickness)

depends upon the power requirement of the system.

Insufficient copper will increase resistance of the PCB, which

will increase heat dissipation.

7. Generally, vias should not be used to route high current paths.

8. While designing the layout of switched controllers, do not use

the auto routing function of the PCB layout software. Auto

routing connects the nets with the same electrical name and

does not account for ideal trace lengths and positioning.

ISL98608IIH Specific Layout Guidelines

1. The input capacitor should be connected to the VIN pin (C1)

with the smallest trace possible. This helps reject high

frequency disturbances and promotes good regulation of the

VBST, VP and VN regulators.

2. The inductor for VBST regulator should be connected between

VIN and LXP pin with a short and wide trace to reduce the

board parasitics. Careful consideration should be made in

selecting the inductor as it may cause electromagnetic

interference, which could affect IC functionality. A shielded

inductor is recommended.

3. Bump VBSTCP is input to the charge pump regulator. This pin

must be connected to VBST on the PCB, so that the boost

regulator provides the input voltage supply for the charge

pump. The CSP bumps for VBST and VBSTCP are A3 and A4

respectively. These two bumps should be connected/shorted

to each other on the PCB with a short and thick trace to avoid

parasitic inductance and resistance. A 10μF/10V capacitor

should be used on trace connecting bump A3 and A4 to

PGND. The distance of the capacitor from the bump A3 and

A4 is critical - it should be placed very close to the IC with a

short and thick trace.

4. The current return path for VBST boost regulator should be

small as possible. The bump A1 is PGND. It is power ground

for VBST regulator. A 10μF/10V capacitor should be placed

between VBST and PGND.

5. Bump D3 is output of the negative charge pump (VN) and

bump D2 is its substrate connection (VSUB). It is highly

recommended that D3 and D2 are shorted together with a

short and thick trace. It is recommended that 2x10μF/10V

capacitors are placed on VN to minimize output ripple.

Additionally, it will help minimize noise that may be coupled

from the high frequency ripple of the charge pump.

6. Bumps B3 is output of the VP regulator. A 10μF/10V

capacitor should be placed between VP and power ground.

7. Bump B4 is charge pump positive connection and bump D4 is

charge pump negative connection. A 10μF/10V capacitor

should be placed between bump B4 and D4. The capacitor

between bump B4 and D4 charges and discharges every cycle

and handles high current surges. The capacitor should be

placed between CP and CN using short and thick trace.

8. Digital input pins ENN, ENP, SDA and SCL should be isolated

from the high di/dt and dv/dt signals. Otherwise, it may cause

a glitch on those inputs.

9. I2C signals, if not used, should be tied to VIN.

10. Analog ground (AGND) and power ground (PGND) of the IC

should be connected to each other. It is crucial to connect

these two grounds at the location very close to the IC. The

regulator should be referenced to the correct ground plane

with the short and thick traces. For example, PGND is the

power ground for VBST regulator, a capacitor should be

placed between VBST and PGND with short and thick trace.

All the ground bumps namely PGND, AGND and PGNDCP

should be connected with a network of ground plane.

11. One plane/layer in the PCB is recommended to be a

dedicated ground plane.

12. The solder pad on the PCB should not be larger than the

solder mask opening for the ball pad on the package. The

optimal solder joint strength, it is recommended a 1:1 ratio

for the two pads.

Figure 64 on page 31 shows the recommended PCB layout for a

typical ISL98608IIH application.

FN8724 Datasheet(PDF) 30 Page - Renesas Technology Corp

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