H8SLASH3024F datasheet(124/841 Pages) RENESAS

124 / 841 page

Section 5 Interrupt Controller

Rev. 2.00 Sep 20, 2005 page 86 of 800

REJ09B0260-0200

SYSCR is initialized to H'09 by a reset and in hardware standby mode. It is not initialized in

software standby mode.

Bit

Initial value

Read/Write

SSBY

R/W

STS2

R/W

STS1

R/W

STS0

R/W

RAME

R/W

NMIEG

R/W

SSOE

R/W

Software standby

Standby timer

select 2 to 0

User bit enable

Selects whether to use the UI bit in

CCR as a user bit or interrupt mask bit

NMI edge select

Selects the NMI input edge

Software standby

output port enable

RAM enable

Bit 3—User Bit Enable (UE): Selects whether to use the UI bit in CCR as a user bit or an

interrupt mask bit.

Bit 3

Description

UI bit in CCR is used as interrupt mask bit

UI bit in CCR is used as user bit

(Initial value)

Bit 2—NMI Edge Select (NMIEG): Selects the NMI input edge.

Bit 2

NMIEG

Description

Interrupt is requested at falling edge of NMI input

(Initial value)

Interrupt is requested at rising edge of NMI input

5.2.2

Interrupt Priority Registers A and B (IPRA, IPRB)

IPRA and IPRB are 8-bit readable/writable registers that control interrupt priority.

H8/3024F Datasheet(PDF) 124 Page - Renesas Technology Corp

H8/3024F Datasheet(HTML) 124 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL