H8SLASH3024F datasheet(121/841 Pages) RENESAS

Part #	H8/3024F

Description	Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

PDF	841 Pages

Scroll/Zoom	100%

Manufacturer	RENESAS [Renesas Technology Corp]

Direct Link	http://www.renesas.com

Logo

121 / 841 page

Section 5 Interrupt Controller

Rev. 2.00 Sep 20, 2005 page 83 of 800

REJ09B0260-0200

Section 5 Interrupt Controller

5.1

Overview

5.1.1

Features

The interrupt controller has the following features:

• Interrupt priority registers (IPRs) for setting interrupt priorities

Interrupts other than NMI can be assigned to two priority levels on a module-by-module basis

in interrupt priority registers A and B (IPRA and IPRB).

• Three-level enabling/disabling by the I and UI bits in the CPU’s condition code register (CCR)

and the UE bit in the system control register (SYSCR)

• Seven external interrupt pins

NMI has the highest priority and is always accepted*; either the rising or falling edge can be

selected. For each of IRQ0 to IRQ5, sensing of the falling edge or level sensing can be selected

independently.

Note: * In the versions with on-chip flash memory, NMI input is sometimes disabled. For details

see 17.9, NMI Input Disabling Conditions.

H8/3024F Datasheet(PDF) 121 Page - Renesas Technology Corp