H8SLASH3024F datasheet(117/841 Pages) RENESAS

Part #	H8/3024F

Description	Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

PDF	841 Pages

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Manufacturer	RENESAS [Renesas Technology Corp]

Direct Link	http://www.renesas.com

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Section 4 Exception Handling

Rev. 2.00 Sep 20, 2005 page 79 of 800

REJ09B0260-0200

4.5

Stack Status after Exception Handling

Figure 4.6 shows the stack after completion of trap instruction exception handling and interrupt

exception handling.

SP–4

SP–3

SP–2

SP–1

SP (ER7) →

SP (ER7)

SP+1

SP+2

SP+3

SP+4

→

SP–4

SP–3

SP–2

SP–1

SP (ER7) →

SP (ER7)

SP+1

SP+2

SP+3

SP+4

→

Before exception handling

After exception handling

Stack area

CCR

CCR*

CCR

After exception handling

Even address

Pushed on stack

a. Normal mode

b. Advanced mode

Legend

PCE:

PCH:

PCL:

CCR:

SP:

Notes:

PC indicates the address of the first instruction that will be executed after return.

Registers must be saved in word or longword size at even addresses.

Ignored at return.

Bits 23 to 16 of program counter (PC)

Bits 15 to 8 of program counter (PC)

Bits 7 to 0 of program counter (PC)

Condition code register

Stack pointer

Figure 4.6 Stack after Completion of Exception Handling

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