H8SLASH3024F datasheet(116/841 Pages) RENESAS

116 / 841 page

Section 4 Exception Handling

Rev. 2.00 Sep 20, 2005 page 78 of 800

REJ09B0260-0200

The on-chip supporting modules that can request interrupts are the watchdog timer (WDT), 16-bit

timer, 8-bit timer, serial communication interface (SCI), and A/D converter. Each interrupt source

has a separate vector address.

NMI is the highest-priority interrupt and is always accepted*. Interrupts are controlled by the

interrupt controller. The interrupt controller can assign interrupts other than NMI to two priority

levels, and arbitrate between simultaneous interrupts. Interrupt priorities are assigned in interrupt

priority registers A and B (IPRA and IPRB) in the interrupt controller.

For details on interrupts see section 5, Interrupt Controller.

Interrupts

External interrupts

Internal interrupts

NMI (1)

IRQ to IRQ (6)

WDT* (1)

16-bit timer (9)

8-bit timer (8)

SCI (8)

A/D converter (1)

Note:

Numbers in parentheses are the number of interrupt sources.

* When the watchdog timer is used as an interval timer, it generates an interrupt

request at every counter overflow.

Figure 4.5 Interrupt Sources and Number of Interrupts

Note: * In the versions with on-chip flash memory, NMI input is sometimes disabled. For details

see 17.9, NMI Input Disabling Conditions.

4.4

Trap Instruction

Trap instruction exception handling starts when a TRAPA instruction is executed. If the UE bit is

set to 1 in the system control register (SYSCR), the exception handling sequence sets the I bit to 1

in CCR. If the UE bit is 0, the I and UI bits are both set to 1 in CCR. The TRAPA instruction

fetches a start address from a vector table entry corresponding to a vector number from 0 to 3,

which is specified in the instruction code.

H8/3024F Datasheet(PDF) 116 Page - Renesas Technology Corp