Analog Integrated Circuit Device Data

36

Freescale Semiconductor

908E624

ADDITIONAL DOCUMENTATION

THERMAL ADDENDUM (REV 3.0)

ADDITIONAL DOCUMENTATION

THERMAL ADDENDUM (REV 3.0)

INTRODUCTION

This thermal addendum is provided as a supplement to the MM908E624

technical datasheet. The addendum provides thermal performance information

that may be critical in the design and development of system applications. All

electrical, application, and packaging information is provided in the datasheet.

Packaging and Thermal Considerations

The MM908E624 is a dual die package. There are two heat sources in the

The stated values are solely for a thermal performance comparison of one

package to another in a standardized environment. This methodology is not meant to and will not predict the performance of a

package in an application-specific environment. Stated values were obtained by measurement and simulation according to the

standards listed below

Standards

54-TERMINAL

SOICW

908E624

DWB SUFFIX

EW (Pb-FREE) SUFFIX

98ASA99294D

54-TERMINAL SOICW

Note

For package dimensions, refer to the

MM908E624 datasheet.

=

.

Table 16. Thermal Performance Comparison

Thermal

Resistance

1 = Power Chip, 2 = Logic Chip [

°C/W]

m = 1,

n = 1

m = 1, n = 2

m = 2, n = 1

m = 2,

n = 2

(1)(2)

40

31

36

(2)(3)

25

16

21

(1)(4)

57

47

52

(5)

21

12

16

Notes:

1.

Per JEDEC JESD51-2 at natural convection, still air

condition.

2.

2s2p thermal test board per JEDEC JESD51-7and

JESD51-5.

3.

Per JEDEC JESD51-8, with the board temperature on the

center trace near the power outputs.

4.

Single layer thermal test board per JEDEC JESD51-3 and

JESD51-5.

5.

Thermal resistance between the die junction and the

exposed pad, “infinite” heat sink attached to exposed pad.

54 Terminal SOIC

0.65 mm Pitch

17.9 mm x 7.5 mm Body