EN25Q64-104FIP datasheet(27/60 Pages) EON

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EN25Q64

Rev. J, Issue Date: 2011/07/07

Dual Output Fast Read (3Bh)

The Dual Output Fast Read (3Bh) is similar to the standard Fast Read (0Bh) instruction except that

data is output on two pins, DQ0 and DQ1, instead of just DQ0. This allows data to be transferred from

the EN25Q64 at twice the rate of standard SPI devices. The Dual Output Fast Read instruction is ideal

for quickly downloading code from to RAM upon power-up or for applications that cache code-

segments to RAM for execution.

Similar to the Fast Read instruction, the Dual Output Fast Read instruction can operation at the highest

possible frequency of FR (see AC Electrical Characteristics). This is accomplished by adding eight

“dummy clocks after the 24-bit address as shown in Figure 13. The dummy clocks allow the device’s

internal circuits additional time for setting up the initial address. The input data during the dummy clock

is “don’t care”. However, the DI pin should be high-impedance prior to the falling edge of the first data

out clock.

Figure 13. Dual Output Fast Read Instruction Sequence Diagram

EN25Q64-104FIP Datasheet(PDF) 27 Page - Eon Silicon Solution Inc.