EN25Q64-104FIP datasheet(11/60 Pages) EON

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EN25Q64

Rev. J, Issue Date: 2011/07/07

OPERATING FEATURES

Standard SPI Modes

The EN25Q64 is accessed through a SPI compatible bus consisting of four signals: Serial Clock (CLK),

Chip Select (CS#), Serial Data Input (DI) and Serial Data Output (DO). Both SPI bus operation Modes 0

(0,0) and 3 (1,1) are supported. The primary difference between Mode 0 and Mode 3, as shown in

Figure 3, concerns the normal state of the CLK signal when the SPI bus master is in standby and data

is not being transferred to the Serial Flash. For Mode 0 the CLK signal is normally low. For Mode 3 the

CLK signal is normally high. In either case data input on the DI pin is sampled on the rising edge of the

CLK. Data output on the DO pin is clocked out on the falling edge of CLK.

Figure 3. SPI Modes

Dual SPI Instruction

The EN25Q64 supports Dual SPI operation when using the “ Dual Output Fast Read and Dual I/O Fast

Read “ (3Bh and BBh) instructions. These instructions allow data to be transferred to or from the Serial

Flash memory at two to three times the rate possible with the standard SPI. The Dual Read instructions

are ideal for quickly downloading code from Flash to RAM upon power-up (code-shadowing) or for

application that cache code-segments to RAM for execution. The Dual output feature simply allows the

SPI input pin to also serve as an output during this instruction. When using Dual SPI instructions the DI

and DO pins become bidirectional I/O pins; DQ0 and DQ1. All other operations use the standard SPI

interface with single output signal.

Quad SPI Instruction

The EN25Q64 supports Quad output operation when using the Quad I/O Fast Read (EBh).This

instruction allows data to be transferred to or from the Serial Flash memory at four to six times the rate

possible with the standard SPI. The Quad Read instruction offer a significant improvement in

continuous and random access transfer rates allowing fast code-shadowing to RAM or for application

that cache code-segments to RAM for execution. The EN25Q64 also supports full Quad Mode function

while using the Enable Quad Peripheral Interface mode (EQPI) (38h). When using Quad SPI instruction

the DI and DO pins become bidirectional I/O pins; DQ0 and DQ1, and the WP# and NC pins become

DQ2 and DQ3 respectively.

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