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ST10F272M Datasheet(PDF) 99 Page - STMicroelectronics |
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ST10F272M Datasheet(HTML) 99 Page - STMicroelectronics |
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99 / 176 page ![]() ST10F272M System reset Doc ID 12968 Rev 3 99/176 20.9 Reset summary The following table summarizes the different reset events. Table 42. Reset event Event RSTIN WDTCON flags Min Max Power-on reset 0 0 N Asynch. 1 ms (VREG) 1.2 ms (reson. + PLL) 10.2 ms (crystal + PLL) - 1 1110 0 1 N Asynch. 1ms (VREG) - 1 1110 1 x x Forbidden xx Y - Hardware reset (asynchronous) 0 0 N Asynch. 500 ns - 0 1110 0 1 N Asynch. 500 ns - 0 1110 0 0 Y Asynch. 500 ns - 0 1110 0 1 Y Asynch. 500 ns - 0 1110 Short hardware reset (synchronous) (1) 1 0 N Synch. Max (4 TCL, 500 ns) 1032 + 12 TCL + max(4 TCL, 500 ns) 0 0110 1 1 N Synch. max (4 TCL, 500 ns) 1032 + 12 TCL + max(4 TCL, 500 ns) 0 0110 10 Y Synch. Max (4 TCL, 500 ns) 1032 + 12 TCL + max(4 TCL, 500 ns) 0 0110 Activated by internal logic for 1024 TCL 11 Y Synch. Max (4 TCL, 500ns) 1032 + 12 TCL + max(4 TCL, 500 ns) 0 0110 Activated by internal logic for 1024 TCL Long hardware reset (synchronous) 10 N Synch. 1032 + 12 TCL + Max(4 TCL, 500 ns) - 0 1110 11 N Synch. 1032 + 12 TCL + Max(4 TCL, 500ns) - 0 1110 10 Y Synch. 1032 + 12 TCL + Max(4 TCL, 500 ns) - 0 1110 Activated by internal logic only for 1024 TCL 11 Y Synch. 1032 + 12 TCL + Max(4 TCL, 500 ns) - 0 1110 Activated by internal logic only for 1024 TCL |
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