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ST10F272M Datasheet(PDF) 36 Page - STMicroelectronics |
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ST10F272M Datasheet(HTML) 36 Page - STMicroelectronics |
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36 / 176 page ![]() Internal Flash memory ST10F272M 36/176 Doc ID 12968 Rev 3 5.5.2 Flash non-volatile write protection I register (FNVWPIR) 5.5.3 Flash non-volatile access protection register 0 (FNVAPR0) 5.5.4 Flash non-volatile access protection register 1 low (FNVAPR1L) FNVWPIR (0x08 DFB0) NVR Reset value: FFFFh 15 14 13 12 11 10 98 765 43 210 Reserved W0P7 W0P6W0P5W0P4W0P3W0P2 W0P1W0P0 - RW RWRWRW RWRW RWRW Table 19. Flash non-volatile write protection I register Bit Name Function 7:0 W0P[7:0] Write protection bank 0/sectors 7-0 (IFlash) These bits, if programmed at 0, disable any write access to the sectors of bank 0 (IFlash) FNVAPR0 (0x08 DFB8) NVR Delivery value: ACFFh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved DBGP ACCP -RW RW Table 20. Flash non-volatile access protection register 0 Bit Name Function 0 ACCP Access protection This bit, if programmed at 0, disables any access (read/write) to data mapped inside IFlash module address space, unless the current instruction is fetched from IFlash. 1DBGP Debug protection This bit, if erased at 1, can be used to by-pass all the protections using the debug features through the test interface. If programmed at 0, on the contrary, all the debug features, the test interface and all the Flash test modes are disabled. Even STMicroelectronics will not be able to access the device to run any eventual failure analysis. FNVAPR1L (0x08 DFBC) NVR Delivery value: FFFFh 15 14 13 12 11 10 98 765 43 210 PDS15 PDS14 PDS13 PDS12 PDS11 PDS10 PDS9 PDS8 PDS7 PDS6 PDS5 PDS4 PDS3 PDS2 PDS1 PDS0 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW |
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