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WM8946ECS/R Datasheet(PDF) 48 Page - Wolfson Microelectronics plc |
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WM8946ECS/R Datasheet(HTML) 48 Page - Wolfson Microelectronics plc |
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48 / 175 page  WM8946 Production Data w PD, July 2012, Rev 4.3 48 Note that SYSCLK must be enabled when writing to the DAC_VU bits. (See “Clocking and Sample Rates” for details of SYSCLK.) The output of the DACs can be digitally muted using the DACL_MUTE or DACR_MUTE bits. Both DACs are muted simultaneously when the DAC_MUTEALL bit is set. A digital soft-mute feature is provided in order to avoid sudden glitches in the analogue signal. When DAC_VOL_RAMP is enabled, then all mute, un-mute or volume change commands are implemented as a gradual volume change in the digital domain. The rate at which the volume ramps up is half of the sample freq (fs/2). The DAC_VOL_RAMP register field is described in Table 25. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R21 (15h) DAC Control 1 8 DAC_MUTEALL 1 DAC Digital Mute for All Channels: 0 = Disable Mute 1 = Enable Mute on all channels R22 (16h) DAC Control 2 4 DAC_VOL_RAMP 1 DAC Volume Ramp control 0 = Disabled 1 = Enabled R23 (17h) Left DAC Digital Vol 12 DAC_VU 0 DAC Volume Update Writing a 1 to this bit will cause Left and Right DAC volume to be updated simultaneously 8 DACL_MUTE 0 Left DAC Digital Mute 0 = Disable Mute 1 = Enable Mute 7:0 DACL_VOL [7:0] 1100_0000 (0dB) Left DAC Digital Volume 0000_0000 = mute 0000_0001 = -71.625dB 0000_0010 = -71.250dB … 1100_0000 = 0dB ... 1111_1111 = +23.625dB (See Table 26 for volume range) R24 (18h) Right DAC Digital Vol 12 DAC_VU 0 DAC Volume Update Writing a 1 to this bit will cause Left and Right DAC volume to be updated simultaneously 8 DACR_MUTE 0 Right DAC Digital Mute 0 = Disable Mute 1 = Enable Mute 7:0 DACR_VOL [7:0] 1100_0000 (0dB) Right DAC volume control 0000_0000 = mute 0000_0001 = -71.625dB 0000_0010 = -71.250dB … 1100_0000 = 0dB ... 1111_1111 = +23.625dB (See Table 26 for volume range) Table 25 DAC Digital Volume Control |
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