WM8946ECSSLASHR datasheet(28/175 Pages) WOLFSON

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WM8946

Production Data

PD, July 2012, Rev 4.3

DIGITAL MICROPHONE INTERFACE

The WM8946 supports a two-channel digital microphone interface. The two-channel audio data is

multiplexed on the IN1L input pin and clocked using a GPIO output. The analogue signal path from

the IN1L pin must be disabled when using the digital microphone interface; this is achieved by

disabling the associated input PGA, (i.e. INPPGAL_ENA= 0).

The Digital Microphone Input, DMICDAT, is provided on the IN1L/DMICDAT pin. The associated

clock, DMICCLK, is provided on a GPIO pin.

The Digital Microphone Input is selected as input by setting the DMIC_ENA bit. When the Digital

Microphone Input is selected, the ADC input is deselected.

The digital microphone interface configuration is illustrated in Figure 11.

Note that the digital microphone may be powered from MICBIAS or from LDOVOUT; care must be

taken to ensure that the respective digital logic levels of the microphone are compatible with the

digital input thresholds of the WM8946. The digital input thresholds are referenced to DBVDD, as

defined in “Electrical Characteristics”.

Figure 11 Digital Microphone Interface

When any GPIO pin is configured as DMICCLK output, the WM8946 outputs a clock which supports

Digital Mic operation at the ADC sampling rate. The ADC and Record Path filters must be enabled

and the ADC sampling rate must be set in order to ensure correct operation of all DSP functions

associated with the digital microphone. Volume control for the Digital Microphone Interface signals is

provided using the ADC Volume Control.

See “Analogue-to-Digital Converter (ADC)” for details of the ADC Enable and volume control

functions. See “General Purpose Input / Output” for details of configuring the DMICCLK output. See

“Clocking and Sample Rates” for the details of the sample rate control.

When the DMIC_ENA bit is set, then the IN1L pin is used as the digital microphone input DMICDAT.

Up to two microphones can share this pin; the two microphones are interleaved as illustrated in

Figure 12.

The digital microphone interface requires that MIC1 (Left Channel) transmits a data bit each time that

DMICCLK is high, and MIC2 (Right Channel) transmits when DMICCLK is low. The WM8946 samples

the digital microphone data in the middle of each DMICCLK clock phase. Each microphone must tri-

state its data output when the other microphone is transmitting.

WM8946ECS/R Datasheet(PDF) 28 Page - Wolfson Microelectronics plc