WM8946ECSSLASHR datasheet(94/175 Pages) WOLFSON

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WM8946

Production Data

PD, July 2012, Rev 4.3

INTERRUPTS

The Interrupt Controller has multiple inputs. These include the GPIO input pins, Temperature sensor

and the LDO Regulator. Any combination of these inputs can be used to trigger an Interrupt (IRQ)

event.

There is an Interrupt Status field associated with each of the IRQ inputs. These are listed within the

System Interrupts Register (R16), as described in Table 61. The status of the IRQ inputs can be read

at any time from this register or else in response to the Interrupt (IRQ) output being signalled via a

GPIO pin.

Individual mask bits can select or deselect different functions from the Interrupt controller. These are

listed within the System Interrupts Mask Register (R19), as described in Table 61. Note that the

status fields remain valid, even when masked, but the masked bits will not cause the Interrupt (IRQ)

output to be asserted.

The Interrupt (IRQ) output represents the logical ‘OR’ of all the unmasked IRQ inputs. The bits within

the System Interrupts Register (R16) are latching fields and, once they are set, they are not reset until

the System Interrupts Register is read. Accordingly, the Interrupt (IRQ) output is not reset until the

System Interrupts Register has been read. Note that, if the condition that caused the IRQ input to be

asserted is still valid, then the Interrupt (IRQ) output will remain set even after the System Interrupts

When GPIO input is used to trigger an Interrupt event, polarity can be set using the GPn_POL bits as

described in Table 59. This allows the IRQ event to be used to indicate a rising or a falling edge of the

external logic signal. If desired, the GPn_INT_MODE bits can be used to select an Interrupt event on

both the rising and falling edges.

The GPIO inputs to the Interrupt Controller are de-bounced to avoid false detections. The timeout

clock (TOCLK) is required for this function. When using GPIO inputs to the Interrupt Controller, the

TOCLK must be enabled by setting the TOCLK_ENA and OSC_CLK_ENA bits as described in

“Clocking and Sample Rates”.

The Interrupt (IRQ) output can be globally masked by setting the IM_IRQ register. The Interrupt is

masked by default.

The Interrupt (IRQ) output may be configured on any of the GPIO pins. See “General Purpose Input /

Output” for details of how to configure GPIO pins for Interrupt (IRQ) output.

The Interrupt control fields are defined in Table 61.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R16 (10h)

System

Interrupts

TEMP_INT

Thermal Interrupt status

0 = Thermal interrupt not set

1 = Thermal interrupt set

This bit is latched when set; it is

cleared when the register is Read.

GP4_INT

GPIO4 Interrupt status

0 = GPIO4 interrupt not set

1 = GPIO4 interrupt set

This bit is latched when set; it is

cleared when the register is Read.

GP3_INT

GPIO3 Interrupt status

0 = GPIO3 interrupt not set

1 = GPIO3 interrupt set

This bit is latched when set; it is

cleared when the register is Read.

GP2_INT

GPIO2 Interrupt status

0 = GPIO2 interrupt not set

1 = GPIO2 interrupt set

This bit is latched when set; it is

cleared when the register is Read.

WM8946ECS/R Datasheet(PDF) 94 Page - Wolfson Microelectronics plc

WM8946ECS/R Datasheet(HTML) 94 Page - Wolfson Microelectronics plc

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