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WM8946ECS/R Datasheet(PDF) 85 Page - Wolfson Microelectronics plc |
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WM8946ECS/R Datasheet(HTML) 85 Page - Wolfson Microelectronics plc |
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85 / 175 page  Production Data WM8946 w PD, July 2012, Rev 4.3 85 EXAMPLE FLL SETTINGS Table 56 provides example FLL settings for generating common SYSCLK frequencies from a variety of low and high frequency reference inputs. FREF FOUT FLL_CLK_ REF_DIV FVCO FLL_N FLL_K FLL_ FRATIO FLL_ OUTDIV FLL_ FRAC 8.000 kHz 22.5792 MHz divide by 1 (0h) 90.3168 MHz 705 (2C1h) 0.6 (9999h) 16 (4h) 4 (1h) 1 8.000 kHz 24.576 MHz divide by 1 (0h) 98.304 MHz 768 (300h) 0.0 (0000h) 16 (4h) 4 (1h) 0 32.768 kHz 22.5792 MHz divide by 1 (0h) 90.3168 MHz 344 (158h) 0.53125 (8800h) 8 (3h) 4 (1h) 1 32.768 kHz 24.576 MHz divide by 1 (0h) 98.304 MHz 375 (177h) 0.0 (0000h) 8 (3h) 4 (1h) 0 768.000 kHz 22.5792 MHz divide by 1 (0h) 90.3168 MHz 14 (00Eh) 0.7 (B333h) 8 (3h) 4 (1h) 1 768.000 kHz 24.576 MHz divide by 1 (0h) 98.304 MHz 16 (010h) 0.0 (0000h) 8 (3h) 4 (1h) 0 1.024 MHz 22.5792 MHz divide by 1 (0h) 90.3168 MHz 88 (058h) 0.2 (3333h) 1 (0h) 4 (1h) 1 1.024 MHz 24.576 MHz divide by 1 (0h) 98.304 MHz 96 (060h) 0.0 (0000h) 1 (0h) 4 (1h) 0 6.144 MHz 22.5792 MHz divide by 1 (0h) 90.3168 MHz 14 (00Eh) 0.7 (B333h) 1 (0h) 4 (1h) 1 6.144 MHz 24.576 MHz divide by 1 (0h) 98.304 MHz 16 (010h) 0.0 (0000h) 1 (0h) 4 (1h) 0 11.2896 MHz 22.5792 MHz divide by 1 (0h) 90.3168 MHz 8 (008h) 0.0 (0000h) 1 (0h) 4 (1h) 0 11.2896 MHz 24.576 MHz divide by 1 (0h) 98.304 MHz 8 (008h) 0.70749 (B51Eh) 1 (0h) 4 (1h) 1 12.000 MHz 22.5792 MHz divide by 1 (0h) 90.3168 MHz 7 (007h) 0.5264 (86C2h) 1 (0h) 4 (1h) 1 12.000 MHz 24.576 MHz divide by 1 (0h) 98.304 MHz 8 (008h) 0.192 (3127h) 1 (0h) 4 (1h) 1 12.288 MHz 22.5792 MHz divide by 1 (0h) 90.3168 MHz 7 (007h) 0.35 (599Ah) 1 (0h) 4 (1h) 1 12.288 MHz 24.576 MHz divide by 1 (0h) 98.304 MHz 8 (008h) 0.0 (0000h) 1 (0h) 4 (1h) 0 13.000 MHz 22.5792 MHz divide by 1 (0h) 90.3168 MHz 6 (006h) 0.94745 (F28Ch) 1 (0h) 4 (1h) 1 13.000 MHz 24.576 MHz divide by 1 (0h) 98.304 MHz 7 (007h) 0.56185 (8FD5h) 1 (0h) 4 (1h) 1 19.200 MHz 22.5792 MHz divide by 2 (1h) 90.3168 MHz 9 (009h) 0.408 (6873h) 1 (0h) 4 (1h) 1 19.200 MHz 24.576 MHz divide by 2 (1h) 98.304 MHz 10 (00Ah) 0.24 (3D71h) 1 (0h) 4 (1h) 1 27.000 MHz 22.5792 MHz divide by 2 (1h) 90.3168 MHz 6 (006h) 0.69013 (B0Adh) 1 (0h) 4 (1h) 1 27.000 MHz 24.576 MHz divide by 2 (1h) 98.304 MHz 7 (007h) 0.28178 (4823h) 1 (0h) 4 (1h) 1 Table 56 Example FLL Settings |
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