WM8946ECSSLASHR datasheet(25/175 Pages) WOLFSON

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Production Data

WM8946

PD, July 2012, Rev 4.3

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

3:2

P_PGAR_SEL

[1:0]

Right Input PGA Non-Inverting Input

Select

00 = Connected to IN2R

01 = Connected to IN1R

10 = Connected to AUX2

11 = Reserved

1:0

P_PGAL_SEL

[1:0]

Left Input PGA Non-Inverting Input

Select

00 = Connected to IN2L

01 = Connected to IN1L

10 = Connected to AUX1

11 = Reserved

Table 2 Input PGA Configuration

MICROPHONE BIAS CONTROL

The WM8946 provides a low noise reference voltage suitable for biasing electret condenser (ECM)

type microphones via an external resistor. Refer to the “Applications Information” section for

recommended components. The MICBIAS voltage is enabled using the MICB_ENA register bit; the

voltage can be selected using the MICB_LVL bit, as described in Table 3.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R2 (02h)

Power

Management 1

MICB_ENA

Microphone Bias Enable

0 = Disabled

1 = Enabled

R39 (27h)

Input Ctrl

MICB_LVL

Microphone Bias Voltage control

0 = 0.9 x LDOVOUT

1 = 0.65 x LDOVOUT

Table 3 Microphone Bias Control

INPUT PGA GAIN CONTROL

The volume control gain for the Left and Right channels can be independently adjusted using the

PGAL_VOL and PGAR_VOL register fields as described in Table 4. The gain range is -12dB to

+35.25dB in 0.75dB steps. The gains on the inverting and non-inverting inputs to the PGAs are

always equal. Each input PGA can be independently muted using the PGA mute bits.

To prevent "zipper noise", a zero-cross function is provided on the input PGAs. When this feature is

enabled, volume updates will not take place until a zero-crossing is detected. In the case of a long

period without zero-crossings, a timeout function is provided. When the zero-cross function is

enabled, the volume will update after the timeout period if no earlier zero-cross has occurred. The

timeout clock is enabled using TOCLK_ENA. See “Clocking and Sample Rates” for the definition of

this bit. Note that the zero-cross function can be supported without TOCLK enabled, but the timeout

function will not be provided in this case.

The PGA_VU bits control the loading of the input PGA volume data. When PGA_VU is set to 0, the

PGA volume data will be loaded into the respective control register, but will not actually change the

gain setting. The left and right input PGA volume settings are both updated when a 1 is written to

PGA_VU; this makes it possible to update the gain of the left and right signal paths simultaneously.

Note that SYSCLK must be enabled when writing to the PGA_VU bits. (See “Clocking and Sample

Rates” for details of SYSCLK.)

WM8946ECS/R Datasheet(PDF) 25 Page - Wolfson Microelectronics plc

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