WM8946ECSSLASHR datasheet(20/175 Pages) WOLFSON

Part #	WM8946ECS/R

Description	Stereo Low-Power CODEC with Video Buffer

PDF	175 Pages

Scroll/Zoom	100%

Manufacturer	WOLFSON [Wolfson Microelectronics plc]

Direct Link	http://www.wolfsonmicro.com

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20 / 175 page

WM8946

Production Data

PD, July 2012, Rev 4.3

Figure 6 Control Interface Timing - 3-wire (SPI) Control Mode (Write Cycle)

Note: The data is latched on the 32

nd falling edge of SCLK after 32 bits have been clocked into the device.

Figure 7 Control Interface Timing - 3-wire (SPI) Control Mode (Read Cycle)

Test Conditions

DCVDD = 1.8V, DBVDD = LDOVDD = SPKVDD = 3.3V, LDOVOUT = 3.0V, GND = 0V,

TA = +25

oC, 1kHz signal, fs = 48kHz, PGA gain = 0dB, 24-bit audio data unless otherwise stated.

PARAMETER

SYMBOL

MIN

TYP

MAX

UNIT

¯¯ falling edge to SCLK rising edge

tCSU

SCLK falling edge to CS

¯¯ rising edge

tCHO

SCLK pulse cycle time

tSCY

200

SCLK pulse width low

tSCL

SCLK pulse width high

tSCH

SDA to SCLK set-up time

tDSU

SDA to SCLK hold time

tDHO

Pulse width of spikes that will be suppressed

tps

SCLK falling edge to SDA output transition

tDL

WM8946ECS/R Datasheet(PDF) 20 Page - Wolfson Microelectronics plc