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WM8946ECS/R Datasheet(PDF) 12 Page - Wolfson Microelectronics plc |
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WM8946ECS/R Datasheet(HTML) 12 Page - Wolfson Microelectronics plc |
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12 / 175 page  WM8946 Production Data w PD, July 2012, Rev 4.3 12 PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Digital Inputs/Outputs Input high level 0.7 DBVDD V Input low level 0.3 DBVDD V Output high level IOL = 1mA 0.8 DBVDD V Output low level IOH = -1mA 0.2 DBVDD V Input capacitance 10 pF Input leakage All digital pins except CIFMODE -900 900 nA CIFMODE pin -90 90 nA LDO Regulator Input voltage LDOVDD 2.4 3.3 3.6 V Output voltage LDOVOUT LDO_REF_SEL = 0 3.0 V Maximum output current (see note) 50 mA Output voltage accuracy ILOAD = 50mA 2 % Quiescent current No Load 55 A Leakage current 1 A PSRR (with respect to LDOVDD) 217Hz 1kHz 40 49 dB Video Buffer Maximum output voltage swing Vom f=100kHz, THD=1% 1.10 1.25 1.50 V pk-pk Voltage gain Av VB_GAIN = 1, RREF=187, RLOAD=75, RSOURCE=75 5.08 6 7.94 dB VB_GAIN = 0, RREF=187, RLOAD=75, RSOURCE=75 -0.92 0 1.94 dB Gain step size 6 dB Differential gain DG Vin = 1V pk-pk -2.0 0.3 +2.0 % Differential phase DP Vin = 1V pk-pk -2.0% 0.7 +2.0 Deg SNR VSNR 40 60 100 dB SYNC tip offset above GND VB_PD = 0 VB_GAIN = 1 0 40 75 mV Third order Low Pass Filter response (referenced to 100kHz) RREF=187, RLOAD=75, RSOURCE=75, 0dB gain 2.4MHz -0.5 0 0.5 dB 5.13MHz -0.5 -0.2 0.5 dB 9.04MHz -3.0 -1.6 0 dB 13.32MHz -11.0 -7.0 -3.0 dB PSRR (with respect to LDOVOUT) 100kHz 60 dB Clocking MCLK frequency 30Hz 27MHz Hz FLL output frequency 2.045 50 MHz FLL lock time 2 ms MICBIAS Bias voltage (changes in proportion to LDOVOUT) MICBIAS MICB_LVL = 0 2.7 V MICB_LVL = 1 1.95 V Bias Current source 3 mA Output noise spectral density 1kHz to 20kHz 15 nV/ Hz PSRR (with respect to LDOVDD) 217Hz 1kHz 70 85 dB |
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