UPSD3312D datasheet(112/272 Pages) STMICROELECTRONICS

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Serial UART interfaces

UPSD33xx

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Doc ID 9685 Rev 7

21.4

More about UART mode 0

Refer to the block diagram in Figure 27 on page 113, and timing diagram in Figure 28 on

page 113.

Transmission is initiated by any instruction which writes to the SFR named SBUF. At the end

of a write operation to SBUF, a 1 is loaded into the 9th position of the transmit shift register

and tells the TX Control unit to begin a transmission. Transmission begins on the following

MCU machine cycle, when the “SEND” signal is active in Figure 28 on page 113.

SEND enables the output of the shift register to the alternate function on the port containing

pin RxD, and also enables the SHIFT CLOCK signal to the alternate function on the port

containing the pin, TxD. At the end of each SHIFT CLOCK in which SEND is active, the

contents of the transmit shift register are shifted to the right one position.

As data bits shift out to the right, zeros come in from the left. When the MSB of the data byte

is at the output position of the shift register, then the '1' that was initially loaded into the 9th

position, is just to the left of the MSB, and all positions to the left of that contain zeros. This

condition flags the TX Control unit to do one last shift, then deactivate SEND, and then set

the interrupt flag TI. Both of these actions occur at S1P1.

Reception is initiated by the condition REN = 1 and RI = 0. At the end of the next MCU

machine cycle, the RX Control unit writes the bits 11111110 to the receive shift register, and

in the next clock phase activates RECEIVE. RECEIVE enables the SHIFT CLOCK signal to

the alternate function on the port containing the pin, TxD. Each pulse of SHIFT CLOCK

moves the contents of the receive shift register one position to the left while RECEIVE is

active. The value that comes in from the right is the value that was sampled at the RxD pin.

As data bits come in from the right, 1s shift out to the left. When the 0 that was initially

loaded into the right-most position arrives at the left-most position in the shift register, it flags

the RX Control unit to do one last shift, and then it loads SBUF. After this, RECEIVE is

cleared, and the receive interrupt flag RI is set.

Modes 1 or

3.6864

9600 Hz

Modes 1 or

1.8432

9600 Hz

Modes 1 or

1.8432

4800 Hz

Table 67.

Commonly used baud rates generated from Timer 1 (continued)

UART

mode

fOSC (MHz)

Desired

baud rate

Resultant

baud rate

Baud rate

deviation

SMOD bit

in PCON

Timer 1

C/T Bit in

TMOD

Timer

mode in

TMOD

TH1

Reload

value

(hex)

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