UPSD3312D datasheet(155/272 Pages) STMICROELECTRONICS

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UPSD33xx

Programmable counter array (PCA) with PWM

Doc ID 9685 Rev 7

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Table 100.

CCON2 register bit definition

Table 101.

CCON3 register (SFR 0FCh, Reset Value 10h)

Table 102.

CCON3 register bit definition

26.3

Operation of TCM modes

Each of the TCM in a PCA block supports four modes of operation. However, an exception is

when the TCM is configured in PWM mode with programmable frequency. In this mode, all

TCM in a PCA block must be configured in the same mode or left to be not used.

26.4

Capture mode

The CAPCOM registers in the TCM are loaded with the counter values when an external pin

input changes state. The user can configure the counter value to be loaded by positive

edge, negative edge or any transition of the input signal. At loading, the TCM can generate

an interrupt if it is enabled.

26.5

Timer mode

The TCM modules can be configured as software timers by enable the comparator. The

user writes a value to the CAPCOM registers, which is then compared with the 16-bit

counter. If there is a match, an interrupt can be generated to CPU.

Bit

Symbol

R/W

Definition

4PCA0CE

R/W

PCA0 Clock Enable

0 = PCA0CLK is disabled

1 = PCA0CLK is enabled (default)

3:0

PCA0PS

[3:0]

R/W

PCA0 Prescaler

fPCA0CLK = fOSC / (2 ^ PCA0PS[3:0])

Divisor range: 1, 2, 4, 8, 16... 16384, 32768

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

–

PCA1CE

PCA1PS3

PCA1PS2

PCA1PS1

PCA1PS0

Bit

Symbol

R/W

Definition

4PCA1CE

R/W

PCA1 Clock Enable

0 = PCA1CLK is disabled

1 = PCA1CLK is enabled (default)

3:0

PCA1PS

[3:0]

R/W

PCA1 Prescaler

fPCA1CLK = fOSC / (2 ^ PCA1PS[3:0])

Divisor range: 1, 2, 4, 8, 16... 16384, 32768

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