UPSD3312D datasheet(151/272 Pages) STMICROELECTRONICS

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UPSD33xx

Analog-to-digital converter (ADC)

Doc ID 9685 Rev 7

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Figure 45.

10-Bit ADC

Table 93.

ACON register (SFR 97h, Reset Value 00h)

ANALOG

MUX

SELECT

ADC OUT - 10 BITS

ADAT 0 REG

ACON REG

CONTROL

10-BIT SAR ADC

ADAT1

REG

ADC0

ADC1

ADC2

ADC3

ADC4

ADC5

ADC6

ADC7

AVREF

P1.0

P1.1

P1.2

P1.3

P1.4

P1.5

P1.6

P1.7

AVREF

AI07856

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

AINTF

AINTEN

ADEN

ADS2

ADS1

ADS0

ADST

ADSF

Table 94.

ACON register bit definition

Bit

Symbol

Function

7AINTF

ADC Interrupt flag. This bit must be cleared with

software.

0 = No interrupt request

1 = The AINTF flag is set when ADSF goes from

'0' to '1.' Interrupts CPU when both AINTF and

AINTEN are set to '1.'

6AINTEN

ADC Interrupt Enable

0 = ADC interrupt is disabled

1 = ADC interrupt is enabled

5ADEN

ADC Enable Bit

0 = ADC shut off and consumes no operating

current

1 = Enable ADC. After ADC is enabled, 16ms of

calibration is needed before ADST Bit is set.

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