UPSD3312D datasheet(148/272 Pages) STMICROELECTRONICS

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Synchronous peripheral interface (SPI)

UPSD33xx

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Doc ID 9685 Rev 7

Table 87.

SPICON1: SPI Interface Control register 1 (SFR D7h, Reset Value 00h)

Table 88.

SPICON1 register bit definition

Table 89.

SPICLKD: SPI Prescaler (Clock Divider) register (SFR D2h, Reset Value

04h)

Table 90.

SPICLKD register bit definition

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

––

TEIE

RORIE

TIE

RIE

Bit

Symbol

R/W

Definition

7-4

–

Reserved

3TEIE

Transmission End Interrupt Enable

0 = Disable Interrupt for Transmission End

1 = Enable Interrupt for Transmission End

2RORIE

Receive Overrun Interrupt Enable

0 = Disable Interrupt for Receive Overrun

1 = Enable Interrupt for Receive Overrun

1TIE

Transmission Interrupt Enable

0 = Disable Interrupt for SPITDR empty

1 = Enable Interrupt for SPITDR empty

0RIE

Reception Interrupt Enable

0 = Disable Interrupt for SPIRDR full

1 = Enable Interrupt for SPIRDR full

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

DIV128

DIV64

DIV32

DIV16

DIV8

DIV4

–

Bit

Symbol

R/W

Definition

7DIV128

0 = No division

1 = Divide fOSC clock by 128

6DIV64

0 = No division

1 = Divide fOSC clock by 64

5DIV32

0 = No division

1 = Divide fOSC clock by 32

4DIV16

0 = No division

1 = Divide fOSC clock by 16

3DIV8

0 = No division

1 = Divide fOSC clock by 8

2DIV4

0 = No division

1 = Divide fOSC clock by 4

1-0

Not Used

–

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